BAST 95 Workshop Program
The Inn at the Tides, Bodega Bay, California
February 7-10, 1995
CONFERENCE COMMITTEE
General Chair: E. J. McCluskey
Program Chair: R. Chandramouli
Program Co-chair: L. Avra
Local Arrangements Chair: H. Hao
Registration Chair: S. Ma
Finance Chair: R. Norwood
Industrial Liaison: K. Ruparel
Publicity Chair: B. Fredrick
ADVISORY COMMITTEE
Chair: E. J. McCluskey
R. Chandramouli
L. Avra R. Aitken
S. Bozorgui-Nesbat
J. Ferguson
PROGRAM COMMITTEE
Chair: R. Chandramouli
Co-chair: L. Avra
Y. El-Ziq
R. Huston
M. Lee
D. Lu
C. Mallipedi
P. Maxwell
M. Purtell
N. Saxena
P. Varma
Tuesday, Feb 7
6:30 PM - 7:30 PM Registration & Reception
7:30 PM Dinner & Talk by Prof. David A. Huffman, UC Santa Cruz
Wednesday, Feb 8
7:15 AM CONTINENTAL BREAKFAST
8:15 AM - 8:20 AM Welcome: E. J. McCluskey, CRC, Stanford University
8:20 AM - 8:30 AM Introduction: R. Chandramouli, Mentor Graphics
8:30 AM - 9:30 AM Session 1 How Much Should You Test and At What Level?
Session Chair: Rob Aitken, HP Labs
1.1 Very High-Level Specification of Test Requirements,
LaNae Avra, CRC, Stanford
1.2 DFT at the HDL Level, Vinod Agarwal, LogicVision
1.3 Accurate and Efficient Fault Simulation of Realistic
CMOS Network Breaks, Haluk Konuk, UC Santa Cruz
1.4 Firing Line: Andre Ivanov, UBC
Amit Majumdar, CrossCheck
9:30 AM-10:30 AM BREAK
10:30 AM - 11:30 AM Session 2 IDDQ Testing -- Switch or Gate Level?
Session Chair: Prab Varma, CrossCheck
2.1 IDDQ Test: Switch vs. Gate Level, Chit Mallipedi,
Sunrise
2.2 Will the Real IDDQ Fault Coverage Please Stand Up?,
Rob Aitken, HP Labs
2.3 Are IDDQ Fault Models and Current Limits Separable?,
John Acken, CrossCheck
2.4 Firing Line: Piero Franco, Synopsys
Tracy Larrabee, UCSC
12:30 PM- 1:30 PM LUNCH
1:30 PM - 2:30 PM Session 3 Prototype Testing and Diagnosis
Session Chair: David Lu, IBM Research Labs
3.1 Processor Chip Bringup and Debug, Hong Hao, Sun
3.2 Planning for Initial Debug of ASIC Embedded Systems,
Ronda Hruby, IBM
3.3 Diagnostic Test Pattern Generation for Small Full Dictionaries,
Brian Chess, UC Santa Cruz
3.4 Firing Line: Eric Larson, Teradyne
Felix Frayman, HP
2:30 PM - 3:30 PM BREAK
3:30 PM - 4:30 PM Session 4 Topics on ATE
Session Chairs: Robert Huston, Credence
Mike Purtell, Megatest
4.1 Progress in Virtual Test, Roger Ball, Cadence
4.2 A Case-Study in the Use of Scan in MicroSparc Testing and Debug,
Jerry Katz, Sun
4.3 Interfaces Between Simulation and Tester,
Tony Taylor, Credence
4.4 Firing Line: Vin Ratford, Mentor Graphics
Sassan Raissi, DTS
7:00 PM DINNER
8:00 PM ENTERTAINMENT
Thursday, Feb 9
7:30 AM CONTINENTAL BREAKFAST
8:30 AM - 9:30 AM Session 5 RAM BIST
Session Chair: Yacoub El-Ziq, Compass Design Automation
5.1 RAMBIST, An Automated Solution to Test Embedded RAMs,
Duraid Musleh, Toshiba
5.2 BIST in Embedded RAMs without Compaction, Nirmal Saxena, HaL
5.3 Embedded RAM Testing: WhatÕs New?, Yacoub El-Ziq, Compass
5.4 Firing Line: James Beusang, Synopsys
Sandeep Bhatia, CrossCheck
9:30 AM - 10:30 AM BREAK
10:30 AM - 11:30 AM Session 6 System-on-a-Chip
Session Chairs: Chit Mallipedi, Sunrise Test Systems
Mike Lee, Fujitsu
6.1 Multi-chip Modules: Testing Challenges, Pat Fasang, Hitachi
6.2 System-on-silicon: Design & Test Issues,
Subrao Shenoy, Cadence
6.3 Testing Strategies for System-on-a-chip Designs,
Farzad Zarrinfar, LSI Logic
6.4 Firing Line: Robert Redinbo, UC Davis
Manzer Masud, Attest
1:00 PM LUNCH
AFTERNOON FREE
7:30 PM - 9:30 PM PANEL DISCUSSION
at Arena Cove Lodge
Will Test Researchers provide solutions for Testing
the coming decade's Submicron designs?
Panel Chair : Edward J. McCluskey, Stanford CRC
Panelist: Fred Buelow, HaL Computer Systems
Tushar Gheewala, CrossCheck Technologies
Farzad Zarrinfar, LSI Logic
Friday, Feb 10
7:30 AM CONTINENTAL BREAKFAST
8:30 AM - 10:00 AM Session 7 Research Activities in Test
Session Chair: Nirmal Saxena, HaL Computers
7.1 CSTP Beyand Stuck-At Faults, Slawomir Pilarski,
Simon Fraser U.
7.2 Transformed Pseudo-Random Patterns for BIST,
Nur Touba, CRC, Stanford
7.3 Fault Simulation for Resistive Bridge Faults, Carl Roth,
UC Santa Cruz
7.4 Design-for-Current-Testability (DFCT) for Dynamic CMOS,
Siyad Ma, CRC, Stanford
7.5 Firing Line: L.-T. Wang, SynTest
Samy Makar, Cirrus Logic
10:00 AM - 11:00 AM BREAK
11:00 AM - 12:00 AM Session 8 DFT Practices - Who Does It and How?
Session Chair: Peter Maxwell, HP Labs
8.1 Practicing DFT: The Good, The Bad, and The Ugly, Marc Levitt, Sun
8.2 Top-Down System DFT - Integrating Multiple Techniques,
Ed Porter, HaL
8.3 Multi-Chip Chips: Physical Design Partitioning Through On-Chip
Virtual Pins, Ben Mathew, Silicon Graphics
8.4 Firing Line: Robert Norwood, Stanford CRC
R. Chandramouli, Mentor Graphics
12:00 AM - 12:10 Noon Closing Remarks
Questionnaire Collection
1:00 PM - 2:00 PM LUNCH
at Poolside