BAST 96 Workshop Program
The Inn at the Tides, Bodega Bay, California
February 6-9, 1996
CONFERENCE COMMITTEE
General Chair: E. J. McCluskey
Program Chair: R. Chandramouli
Local Arrangements Chair: H. Hao
Registration Chair: R. Norwood
Finance Chair: T. Y. Chang
Publicity Chair: P. Fasang
Graphics Chair: S. Ma
Entertainment Chair: D. Lu
Tuesday, Feb 6
6:30 PM - 7:30 PM Registration & Reception
7:30 PM Dinner & Talk by Bob Pease, National Semiconductor
Wednesday, Feb 7
7:15 AM CONTINENTAL BREAKFAST
8:15 AM - 8:20 AM Welcome: E. J. McCluskey, CRC, Stanford University
8:20 AM - 8:25 AM Introduction: R. Chandramouli, LogicVision
8:30 AM - 9:30 AM Session 1 BIST in the Submicron Zone
Session Chair: E. J. McCluskey, CRC, Stanford University
1.1 The Creature from the Deep Submicron Lagoon,
Bernd Koenemann, LogicVision
1.2 Test Point Insertion for a Specified Set of Test Patterns,
Nur Touba, CRC, Stanford University
1.3 BIST Algorithms & Implementation in HaL's SPARC64 Processor,
Nirmal Saxena, Hal Computers
1.4 Firing Line: Tracy Larrabee, UC Santa Cruz
Shridar Mukund, Cirrus Logic
9:30 AM-10:30 AM BREAK
10:30 AM - 11:30 AM Session 2 Synthesis For Test: At what level
Session Chair: R. Chandramouli, LogicVision
2.1 Synthesis-for-Scan and Scan Chain Ordering,
Rob Norwood, CRC, Stanford University
2.2 Low Overhead Scan Design Methodologies,
Mike Lee, Fujitsu Labs
2.3 Integration of Hierarchical Test Generation with Behavioral Synthesis
of Controller and Data Path Circuits,
Sandeep Bhatia, CrossCheck
2.4 Firing Line: Micaela Serra, University of Victoria
Prab Varma, CrossCheck
12:00 PM- 1:00 PM LUNCH
at Poolside (weather permitting)
1:30 PM - 2:30 PM Session 3 Failures and Faults: How deep should we get in
Session Chair: Robert Redinbo, UC Davis
3.1 Physical Design for Testability- How can it be measured,
Joel Ferguson, UC Santa Cruz
3.2 Failures in the Analog Domain, Naveena Nagi,
LogicVision
3.3 Combining Realistic Fault Models and Industrial Designs:
Practical Experiences in Technology Transfer,
Carl Roth, UC Santa Cruz
3.4 Firing Line: Wu Tung Cheng, Mentor Graphics
Farzad Zarrinfar, LSI Logic
2:30 PM - 3:30 PM BREAK
3:30 PM - 4:30 PM Session 4 Test Generation
Session Chair: Jon Muzio, University of Victoria
4.1 Checking Experiments to Test D Flip-flops,
Samy Makar, Cirrus Logic
4.2 Issues in IDDQ Testing, Paul Thadikaran, CrossCheck
4.3 Combining Stuck-At, Delay, and IDDQ tests,
Siyad Ma, AMD
4.4 Firing Line: Jonathan Chang, CRC Stanford
Nirmal Saxena, Hal Computers
7:00 PM DINNER
8:00 PM FUN & GAMES
Thursday, Feb 8
7:30 AM CONTINENTAL BREAKFAST
8:30 AM - 9:30 AM Session 5 Testability Standards: Are they here to stay
Session Chair: Pat Fasang, Hitachi
5.1 Testability Standards in Custom Design,
Bulent Dervisoglu, Silicon Graphics
5.2 Issues in ASIC Manufacturing, Nick Sporch, LSI Logic
5.3 BIST in a Workstation DFT Methodology,
Brent Miller, HaL Computers
5.4 Firing Line: Kevin Giebel, Teradyne
L. T. Wang, Syntest
9:30 AM - 10:30 AM BREAK
10:30 AM - 11:30 AM Session 6 Should Test Be Considered a Cost
Session Chair: Ed Porter, HaL Computers
6.1 Test Economics - What's It Worth?,
Prab Varma, CrossCheck
6.2 Cost of Ownership for Test Methodology,
Farzad Zarrinfar, LSI Logic
6.3 The Economics of Manufacturing Testing Beyond the Silicon,
Felix Frayman, HP Labs
6.4 Firing Line: Eric Larson, Teradyne
Bob Huston, Credence
12:00 PM - 1:00 PM LUNCH
at Poolside (weather permitting)
AFTERNOON FREE
7:30 PM - 9:30 PM PANEL DISCUSSION
at Bay View Room
What is the crossover point for test cost
over process and design cost?
Panel Chair : Edward J. McCluskey, Stanford CRC
Panelist: Ed Porter, HaL Computer Systems
Bulent Dervisoglu, Silicon Graphics
Bob Huston, Credence Systems
Bernd Koenemann, LogicVision
Friday, Feb 9
7:30 AM CONTINENTAL BREAKFAST
8:30 AM - 10:00 AM Session 7 Automation of Debug and Diagnostics
Session Chair: Rochit Rajsuman, LSI Logic
7.1 Failure Analysis for Full Scan Design,
Arun Gunda, LSI Logic
7.2 Automating Failure Diagnosis of Scan-Based Circuits,
John Waicukauski, Mentor Graphics
7.3 Diagnosis: Beyond the Byzantine Generals Problem,
David Lavo, UC Santa Cruz
7.5 Firing Line: Bulent Dervisoglu, Silicon Graphics
Bernd Koenemann, LogicVision
10:00 AM - 10:30 AM BREAK
10:30 AM - 11:30 AM Session 8 Verification: A name with many faces
Session Chair: Nirmal Saxena, HaL Computers
8.1 Formal Verification Challenges for m-Processors,
Dian Yang, Silicon Graphics
8.2 Silicon Verification Using Logic Simulation Generated Test Vectors,
Kirit Khichadia, Simutest
8.3 Trouble with X's : Simulation versus Synthesis
David Lu, IBM
8.4 Firing Line: Brian Chess, Hewlett-Packard
Wern-Yan Koe, Fujitsu
11:30 AM - 12:00 Noon Closing Remarks
Questionnaire Collection
12:30 PM - 1:30 PM LUNCH
at Poolside