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Bibliography of Stanford Publications

Hyperlinked publications are in portable document format (*.pdf) or postscript (*.ps) format.
PhD Theses
Papers
List of Abbreviations



PhD Theses (1970 - present, reverse chronological order)

Last known employer shown in parentheses.


Lee, Donghwi, Launch Delay Test, April 2008. (NVIDIA)

Cho, Kyoung Youn (Ken), A New Test Metric and a New Scan Architecture for Efficient VLSI Testing, December 2007. (NVIDIA)

Volkerink, Erik, Design for Testability Techniques for Scan Compression, June 2004. (Agilent)

Chmelar, Erik, The Test and Diagnosis of FPGAs, June 2004. (LSI Logic)

Al-Yamani, Ahmad, Deterministic Built-In Self-Test for Digital Circuits, April 2004. (King Fahd University of Petroleum and Minerals, Saudi Arabia)

Li, James Chien-Mo, Test and Diagnosis of Open Defects in Digital CMOS Integrated Circuits and Appendix, June 2002. (National Taiwan University)

Yu, S.-Y, Fault Tolerance in Adaptive Real-Time Computing Systems, Dec. 2001. (nVidia)

Huang, W.-J., Dependable Computing Techniques for Reconfigurable Hardware, June 2001. (Velio Communications, Inc.)

Shirvani, P. P., Fault-Tolerant Computing for Radiation Environments, June 2001. (Atheros)

Oh, N., Software Implemented Hardware Fault Tolerance, Dec. 2000. (Synopsys)

Mitra, S., Diversity Techniques for Concurrent Error Detection, June 2000. (Stanford University)

Chang, T. Y. J., Voltage Screens for Early-Life Failures in CMOS Integrated Circuits, June 1998. (Intel)

Norwood, R. B., Synthesis-for-Scan: Reducing Scan Overhead with High-Level Synthesis, December 1997. (John Brown University)

Makar, S., Checking Experiments for Scan Chain Latches and Flip-Flops, June 1996. (Azul Systems)

Touba, N., Synthesis Techniques for Pseudo-Random Built-In Self-Test, June 1996. (University of Texas at Austin)

Ma, S., Testing BiCMOS and Dynamic CMOS Logic, June 1995. (Zettacom)

Franco, P., Testing Digital Circuits for Timing Failures by Output Waveform Analysis, June 1994. (Hanna Instruments, Inc.)

Avra, L., Synthesis Techniques for Built-in Self-Testable Designs, June 1994. (Cadence)

Hao, H., Electrical Failure Modes in CMOS Logic Integrated Circuits, 1993. (LSI Logic)

Saxena, N., Test and Checker Data Compaction," 1991. (NVidia)

Millman, S. D., Nonclassical Faults in CMOS Digital Integrated Circuits," 1989. (Motorola)

Udell, U., Pseudo-Exhaustive Testing of Digital Integrated Circuits," 1988. (NCR)

Wagner, K., Digital Circuits: Random Testing and Testing Issues," 1987. (S3)

Wang, L.-T., Circuits for Built-In Self-Test," 1987. (SynTest)

Liu, D., Testable Structures for CMOS VLSI Circuits," 1987. (Quickturn)

Cortes, M. L., Temporary Failures in Digital Circuit: Experimental Results and Fault Modelling, 1987. (Telebras, Brazil)

Amer, H., Computer Systems: Modeling and Reliability Issues," 1987. (University of Cairo, Egypt)

Hughes, J. L. A., Reliable Digital Systems: Multiple Fault Detection and Totally Self-Checking Comparators, 1986. (Georgia Technological University)

Mahmood, A., Concurrent Checking Using Watchdog Processors, 1986. (Amdahl)

Bozorgui-Nesbat, S., Design for Testability: Random Logic and Programmable Logic Arrays, 1985. (Sun Microsystems)

Hassan, S., Design for Testability Techniques Using Signature Analysis, 1984. (UMS, Pakistan)

Namjoo, M., Concurrent Testing at the Computer System Level, 1983. (Sun Microsystems)

Khakbaz, J., Testing and Concurrent Checking for PLA's and Related Checker Design Issues, 1983. (Tandem)

Butner, S., Failures in Computers: A Study of Their Characteristics and a Tolerance Technique, 1981. (University of Californa, Sana Barbera)

Lu, D., Concurrent Testing and Checking in Computer Systems, 1981. (IBM)

Blount, M. L., Probabilistic Fault Diagnosis Models for Digital Systems, 1978. (IBM)

Beaudry, M. D., Performance Considerations for the Reliability Analysis of Computing Systems, 1978. (PFS)

Savir, J., Detection of Intermittent Failures in Combinational Circuits, 1977. (IBM)

Betancourt, R., Analysis and Synthesis of Sequential Circuits Using Clocked Flip-Flops, 1977. (Altera)

Usas, A. M., Error/Management in Digital Computer Input/Output Systems, 1976. (Tandem)

Shedletsky, J. J., Error Latency in Digital Circuits, 1976. (IBM)

Parker, K. P., Probabilistic Test Generation, 1976. (Hewlett Packard)

Kolupaev, S. G., Cutting Planes and Self-Checking Networks, 1976. (unknown)

Price, T. G. Jr., Probability Models of Computer Systems, 1975. (IBM)

O.-Dias, F. J., Multiple Fault Analysis in Combinational Logic Circuits, 1975. (Brazil)

Ogus, R. C., Design and Evaluation of Ultra-Reliable Hybrid Redundant Digital Systems, 1975. (Xerox)

Mei, K. C. Y., Dominance Relations of Stuck-at and Bridging Faults in Logic Networks, 1975. (PLX Technology)

Losq, J., Modeling and Reliability of Redundant Digital Systems, 1975. (Consultant)

Wang, D. T., An Algorithm for the Generation of Test Sets for Combinational Logic Networks, 1974. (IBM)

Wakerly, J. F., Low-Cost Error Detection Techniques for Small Computers, 1974. (Cisco Systems, Inc.)

Svobodova, L., Computer Performance Measurement and Evaluation Methods: Analysis and Applications, 1974. (IBM)

Shapiro, G. N., A Functional Approach to Structured Combinational-Logic Design, 1974. (unknown)

Mitarai, H., The Use of Semiconductor Read-Only Memory for Logic, 1974. (Canon)

Abraham, J. A., Reliability Analysis of Digital Systems Protected by Massive Redundancy, 1974. (University of Texas)

Salisbury, A. B., The Evaluation of Microprogram Implemented Emulators, 1973. (U.S. Army)

Boute, R. T., Faults in Sequential Machines: Algebraic Properties and Detection Methods, 1973. (University of Gent, Belgium)

Siewiorek, D.P ., Fault-Tolerant Computers Using Self-Diagnosis and Hybrid Redundancy, 1972. (Carnegie Mellon University)

Fuller, S. H., The Analysis and Scheduling of Devices Having Rotational Delays, 1972. (DEC)

Chesarek, D. J., Fault Detecting Experiments for Sequential Machines, 1972. (IBM)

Chamberlin, D. D., Parallel Implementation of a Single Assignment Language, 1971. (IBM)

Clegg, F. W., Algebraic Properties of Faults in Logic Networks, 1970. (Consultant)

Bredt, T. H., Control of Parallel Processes, 1970. (Menlo Ventures)



Papers (1969 - present, alphabetical order by first author)


Abraham, J. A., ``A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks," IEEE Trans. Comput., Vol. C-24, No. 5, pp. 578-584, May 1975. (CSL TN 32)

Abraham, J. A., and D. P. Siewiorek, ``Reliability Modeling of NMR Networks," CSL TR 56.

Abraham, J. A., ``Bibliography on Computer Network Reliability," CSL TN 37.

Abraham, J. A., and D. P. Siewiorek, ``An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks," IEEE Trans. Comput., C-23, No. 7, pp. 682-693, July 1974.

Al-Yamani, A. A., N. Oh, and E. J. McCluskey, ``Algorithm-Based Fault Tolerance: A Performance Perspective Based on Error Rate," DSN'01.

Al-Yamani, A. A., N. Oh, and E. J. McCluskey, ``Performance Evaluation of Checksum-Based ABFT," DFT'01.

Al-Yamani, A. A., and E. J. McCluskey, ``Low-Overhead Built-In BIST Reseeding," TRP'02.

Al-Yamani, A. A., S. Mitra, and E. J. McCluskey, ``Techniques for Testing Digital Circuits with Constraints," DFT'02.

Al-Yamani, A. A., S. Mitra, and E. J. McCluskey, ``Avoiding Illegal States in Pseudorandom Testing of Digital Circuits," CRC TR 02-02.

Al-Yamani, A. A., and E. J. McCluskey, ``Built-In Reseeding for Built-In Self Test," CRC TR 02-03.

Al-Yamani, A. A., and E. J. McCluskey, ``Built-In Reseeding for Serial BIST," VTS'03.

Al-Yamani, A. A., S. Mitra, and E. J. McCluskey, ``BIST Reseeding with Very Few Seeds," VTS'03.

Al-Yamani, A. A., and E. J. McCluskey, ``Seed Encoding for LFSRs and Cellular Automata," DAC'03.

Al-Yamani, A. A., S. Mitra, and E. J. McCluskey, ``Optimized Reseeding by Seed Ordering and Encoding," TCAD'04.

Al-Yamani, E. Chmelar, and M. Grinchuk, ``Segmented Addressable Scan Architecture," VTS'05.

Amer, H. H., and E. J. McCluskey, ``Calculation of the Coverage Parameter for the Reliability Modeling of Fault-Tolerant Computer Systems," ISCAS'86, pp. 1050-1053. (CRC TR 86-1)

Amer, H. H., and R. K. Iyer, ``Effect of Uncertainty in Failure Rates on Memory System Reliability," IEEE Trans. Reliability, Vol. R-35, No. 4, pp. 377-379, Oct. 1986.

Amer, H. H., ``Strongly Fault-Secure Switch for Self-Purging Redundant Systems," Proc. Twentieth Annual Asilomar Conference on Signals, Systems and Computers , Monterey, CA, pp. 312-316, Nov. 1986.

Amer, H. H., and E. J. McCluskey, ``Calculation of Coverage Parameter," IEEE Trans. Reliability, Spec. Issue on Fault Tolerant Comput., Vol. R-36, No. 2, pp. 194-198, June 1987.

Amer, H. H., and E. J. McCluskey, ``Weighted Coverage in Fault-Tolerant Systems," Proc. Reliability and Maintainability Symp., Philadelphia, PA, pp. 187-191, Jan. 1987. (CRC TR 87-8)

Amer, H. H., and E. J. McCluskey, ``Modeling the Effect of Chip Failures on Cache Memory Systems," Proc. Third Int. Conf. Data Eng., Los Angeles, CA, pp. 340-346, Feb. 1987.

Amer, H. H., and E. J. McCluskey, ``Latent Failures and Coverage in Fault-Tolerant Systems," Proc. Phoenix Conf. Comput. and Comm., Scottsdale, AZ, pp. 89-93, Feb. 1987.

Amer, H. H., M. L. Côrtes, and E. J. McCluskey, ``Inadequacy of Conventional Dynamic Recovery Mechanisms in the Presence of Temporary Failures," CRC TR 87-11.

Amer, H. H., ``Computer Systems: Modeling and Reliability Issues," CRC TR 87-16.

Amer, H. H., M. L. Côrtes, and E. J. McCluskey, ``Robust Dynamic Recovery Mechanisms," ICCD'87, pp. 310-313.

Amer, H. H., and E. J. McCluskey, ``Safe and Unsafe faults in CMOS Exclusive-Or Gates with Gate Oxide Shorts," CRC TR 88-8.

Andrews, D. M., A. Mahmood, and E. J. McCluskey, ``Dynamic Assertion Testing of Flight Control Software," CRC TR 85-15.

Andrews, D. M., and E. J. McCluskey, ``The Measurement and Modeling of Computer Reliability as Affected by System Activity," CRC TR 85-18.

Andrews, D. M., A. Mahmood, and E. J. McCluskey, ``A Methodology for Testing Fault-Tolerant Software," CRC TR 85-22.

Andrews, D. M., ``Automation of Assertion Testing: Grid and Adaptive Techniques," HICSS'85, Vol. 2, pp. 692-699. (CRC TR 84-12)

Archambeau, E. C., and E. J. McCluskey, ``Fault Coverage of Pseudo-Exhaustive Testing," FTC'84, pp. 141-145. (CRC TR 83-20 and 84-2)

Archambeau, E. C., ``Network Segmentation for Pseudo-Exhaustive Testing," CRC TR 85-10.

Avra, L., and E. J. McCluskey, ``Behavioral Synthesis of Testable Systems with VHDL," COMPCON'90, pp. 410-415. (CRC TR 89-10)

Avra, L., and E. J. McCluskey, ``On the Behavioral Synthesis of Testable Systems with VHDL," CRC TR 90-2.

Avra, L., ``Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths," ITC'91, pp. 463-472. (CRC TR 90-9 and 91-5)

Avra, L., ``Orthogonal Built-In Self-Test," COMPCON'92, pp. 452-457.

Avra, L. J., and E. J. McCluskey, ``Synthesizing for Scan Dependence in Built-In Self-Testable Designs," ITC'93, pp. 734-743. (CRC TR 93-2)

Avra, L. J., and E. J. McCluskey, ``Synthesis for Scan Dependence in Built-In Self-Testable Designs," CRC TR 94-2.

Avra, L. J., L. Gerbaux, J.-C. Giomi, F. Martinolle, and E. J. McCluskey, ``A Synthesis-for-Test Design System," CRC TR 94-3.

Avra, L. J., ``Synthesis Techniques for Built-In Self-Testable Designs," CRC TR 94-7.

Avra, L. J., and E. J. McCluskey, ``High-Level Synthesis of Testable Designs: An Overview of University Systems," ITC'94, Test Synthesis Seminar, TS Paper 1.1. (CRC TR 94-8)

Avra, L. J., and E. J. McCluskey, ``An Overview of the Stanford TOPS (Totally-Optimized Synthesis) Tool," Third Int. Test Synthesis Workshop, Santa Barbara, CA, May 6-8, 1996.

Beaudry, M. D.,``Performance Related Reliability Measures for Computing Systems," FTC'77, pp. 16-21. (CSL TN 101)

Beaudry, M. D., ``Dual Redundancy - a Survey," CSL TN 93.

Beaudry, M. D., ``A Statistical Study of Service Interruptions at the SLAC Triplex Multiprocessor," CSL TR 141.

Beaudry, M. D., ``Performance-related Reliability Measures for Computing Systems," IEEE Trans. Comput., pp. 540-547, June 1978. (CSL TN 101)

Beaudry, M. D., ``Performance Considerations for Reliability Analysis - a Statistical Case Study," FTC'78, p. 198. (CSL TN 126)

Beaudry, M. D., ``A Statistical Analysis of Failures in the SLAC Computing Center," COMPCON'79, pp. 49-52.

Beaudry, M. D., ``Stochastic Behavior of Failures in Computing Systems," CSL TN 172.

Betancourt, R., ``Derivation of Minimum Test Sets for Unate Logical Circuits," CSL TN 3.

Betancourt, R., ``Derivation of Minimal Test Sets For Unate Logical Circuits," IEEE Trans. Comput., C-20, No. 11, Nov. 1971, pp. 1264-1269.

Betancourt, R., ``Analysis of Sequential Circuits Using Clocked Flip-flops," CSL TN 82.

Betancourt, R., ``Computer Programs for 'Reliability Evaluation Programs' - A Survey," CSL TN 119.

Blount, M. L., ``Probabilistic Treatment of Diagnosis in Digital Systems," FTC'77, pp. 72-77. (CSL TN 102)

Blount, M. L., ``A Probabilistic Model for Diagnosis in Digital Systems," CSL TR 144.

Blount, M. L., ``On the Calculation of the Parameter Set for the Probabilistic Diagnosis Model," CSL TN 139.

Blount, M. L., ``Modeling of Diagnosis in Fail-Softly Computer Systems," FTC'78, pp. 53-58, and Design Automation & Fault-Tolerant Computing, Vol. III, Issue 3/4, pp. 171-189, 1980. (CSL TN 123)

Boley, D., G. H. Golub, S. Makar, N. Saxena, and E. J. McCluskey, ``Backward Error Assertions for Checking Solutions to Systems of Linear Equations," Numerical Analysis Project, Manuscript NA-89-12, Nov. 1989.

Boley, D., G. H. Golub, S. Makar, N. Saxena, and E. J. McCluskey, ``Floating Point Fault-Tolerance with Backward Error Assertions," IEEE Trans. Comput., Special Issue on Fault-Tolerant Computing, pp. 302-311, Feb. 1995.

Bose, B., ``On Unordered Codes," FTC'87, pp. 102-107.

Boute, R. T., ``Algorithms for Combinational Fault Equivalence Using LISP," CSL TN 9.

Boute, R. T., and E. J. McCluskey, ``Fault Equivalence in Sequential Machines," Symp. on Computers and Automata, Polytechnic of Brooklyn, Apr. 13-15, 1971, pp. 483-507. (CSL TR 15)

Boute, R. T., ``Note on the Characterization of Rings of Integers in View of Arithmetic Codes," CSL TN 22.

Boute, R. T., ``Adaptive Design Methods for Checking Sequences," CSL TR 30.

Boute, R. T., ``Algebraic Properties of Test Sequences and Fault Relations," CSL TR 37.

Boute, R. T., ``Equivalence and dominance relations between output faults in sequential machines," Tech. Rpt. No., 38, SU-SEL-72-052, Stanford University, Stanford, CA, Nov. 1972.

Boute, R. T., ``Properties of Memory Faults in Sequential Machines," CSL TR 39.

Boute, R. T., ``Checking Experiments for Output Faults," CSL TR 40.

Boute, R. T., ``Fault Detection in Fundamental Mode Circuits," CSL TR 41.

Boute, R. T., ``Optimal and Near-optimal Checking Experiments for Output Faults in Sequential Machines," IEEE Trans. Comput., C-23, No. 11, Nov. 1974, pp. 1207-1213.

Boute, R. T., ``Distinguishing Sets for Optimal State Identification in Checking Experiments," IEEE Trans. Comput., C-23, No. 8, Aug. 1974, pp. 874-878.

Boute, R. T., ``Algebraic Properties of Testing and Diagnosing Sequences," FTC'75, pp. 242.

Bozorgui-Nesbat, S., and E. J. McCluskey, ``Structured Design for Testability to Eliminate Test Pattern Generation," FTC'80, pp. 158-163. (CSL TN 177)

Bozorgui-Nesbat, S., ``LIST and Documentation of the PLA Testability Program," CRC TR 85-9.

Bozorgui-Nesbat, S., and E. J. McCluskey, "Verification Testing of Programmable Logic Arrays," CRC TR 85-19.

Bozorgui-Nesbat, S., and E. J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," ITC'84, pp. 856-865, and IEEE Trans. Comput., Vol. C-35, No. 4, pp. 379-383, Apr. 1986. (CRC TR 84-8)

Bozorgui-Nesbat, S., and E. J. McCluskey, "Design for Delay Testing of Programmable Logic Arrays," ICCAD'84, pp. 146-148. (CRC TR 84-10)

Brand, K., S. Mitra, E. Volkerink and E.J. McCluskey, ``Speed Clustering of Integrated Circuits," ITC'04, pp. 1128-1137, 2004.

Bredt, T. H., and E. J. McCluskey, ``Analysis and Synthesis of Control Mechanisms for Parallel Processes," Proc., Symposium on Parallel Processor Systems, Technologies and Applications, Monterey, CA, June 25-27, 1969. (These Proceedings came out as a book in 1970: Parallel Processor Systems, Technologies, and Applications, L.C. Hobbs, D. J. Theis, J. Trimble, H. Titus and I. Highbury, eds., Spartan Books, New York, New York, 1970. The article appears on pp. 287-295 of this book).

Bredt, T. H., and E. J. McCluskey, ``A Model for Parallel Computer Systems," CSL TR 5.

Bredt, T. H., and E. J. McCluskey, ``On the Necessity of Mutual Exclusion for Mutual Exclusion," CSL TN 6.

Bredt, T. H., ``Analysis of Parallel Systems," IEEE Trans.Comput., C-20, No. 11, Nov. 1971, pp. 1403-1407.

Bredt, T. H., ``Design of Concurrent Programs," (abstract), Proc., Fifth Princeton Conf. on Information Sciences and Systems, Princeton University, Princeton, NJ, Mar. 1971, p. 300.

Bredt, T. H., ``Analysis of Operating System Interactions," Proc., AICA Cong. on Theoretical Informatics, University of Pisa, Pisa, Italy, Mar. 1973, pp. 255-281.

Bredt, T. H., and A. R. Saxena, ``Hierarchical Design Methods for Operating Systems," COMPCON'74, pp. 153-156.

Butakov, E. A., and M. S. Posherstnick, ``Design of Two-Level Fault-Tolerant Networks from Threshold Elements," CSL TR 134.

Butner, S. E., and R. K. Iyer, ``A Statistical Study of Reliability and System Load at SLAC," FTC'80, pp. 207-209. (CSL TR 188) (CSL TN 177)

Butner, S. E., ``A Universal Slice Element for Triple Time Redundant Systems," CRC TR 81-9.

Butner, S. E., ``Triple Time Redundancy, Fault-masking in Byte-Sliced Systems," CRC TR 81-2.

Butner, S. E., ``A Constructive Approach to Fault Tolerance in VLSI-Based Systems," Proc., 1981 Int. Conf. on Parallel Processing, pp. 264-265, Bellaire, MI, Aug. 25-28, 1981.

CRC Faculty and Staff, ``Center for Reliable Computing," CSL TN 112.

Chamberlin, D. D., ``The 'Single Assessment' Approach to Parallel Processing," Proc., AFIP Conf., Vol. 39, pp. 263-269, Las Vegas, NV, Nov. 16-18, 1971.

Chang, T. Y. J., and E. J. McCluskey,``Quantitative Analysis of Very-Low-Voltage Testing," VTS'96, pp. 332-337.

Chang, T. Y. J. , and E. J. McCluskey, ``Detecting Delay Flaws by Very-Low-Voltage Testing," ITC'96, pp. 367-376.

Chang, T. Y. J., and E. J. McCluskey, `` SHOrt Voltage Elevation (SHOVE) Test," 1996 IEEE Int. Workshop on IDDQ Testing, pp. 45-49, Washington, DC, Oct. 24-25, 1996.

Chang, T. Y. J ., and E. J. McCluskey, ``SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs," VTS'97, pp. 446-451. ((CRC TN 96-2)

Chang, T. Y. J., and E. J. McCluskey, ``Detecting Bridging Faults in CMOS Dynamic Circuits," 1997 Int. Workshop on IDDQ Testing, pp. 106-109, Washington, DC, Nov. 5-6, 1997.

Chang, T. Y. J., C. W. Tseng, Y. C. Chu, S. Wattal, M. Purtell, and E. J. McCluskey, ``Experimental Results for IDDQ and VLV Testing," VTS'97, pp. 118-123.

Chang, T. Y. J., C.W. Tseng, C. M. J. Li, M. Purtell, and E. J. McCluskey, ``Analysis of Pattern-Dependent and Timing-Dependent Failures in an Experimental Test Chip," ITC'98, pp. 184-193.

Chang, T. Y. J., and E. J. McCluskey, ``Detecting Resistive Shorts for CMOS Domino Circuits," ITC'98, pp. 890-899.

Cheng, K. Y., and E. J. McCluskey, ``Analysis of Fail-All-Test-Set CUTs and Fail-Some-Test-Set CUTs in an Experimental Test Chip," CRC TR 99-2, Aug. 1999.

Chin, C. K., and E. J. McCluskey, ``Weighted Pattern Generation for Built-in Self-Test," CRC TR 84-7.

Chin, C. K., and E. J. McCluskey, ``Test Length for Pseudorandom Testing," ITC'85, pp. 94-99; IEEE Trans. Comput., Vol. C-36, No. 2, pp. 252-256, Feb. 1987. (CRC TR 85-11 and 85-14)

Chmelar, E., ``FPGA Interconnect Delay Fault Testing," ITC'03.

Chmelar, E., ``Subframe Multiplexing: FPGA Manufacturing Test Time Reduction," CRC TR 04-01, Mar. 2004.

Chmelar, E. and S. Toutounchi, ``FPGA Bridging Fault Detection and Location via Differential IDDQ," VTS'04.

Chmelar, E., ``Minimizing the Number of Test Configurations for FPGAs," ICCAD'04.

Cho, K. Y., S. Mitra, and E. J. McCluskey, ``Gate Exhaustive Testing," ITC'05, Paper 31.3, 2005.

Cho, K. Y. and E. J. McCluskey, ``Test Set Reordering Using the Gate Exhaustive Test Metric," VTS'07, pp. 199-204, 2007.

Cho, K. Y., S. Mitra, and E. J. McCluskey, `California Scan Architecture for High Quality and Low Power Testing," Proc. Int. Test Conf., paper 25.3, 2007.

Clegg, F. W., and E. J. McCluskey, ``Algebraic Properties of Faults in Logic Networks," CSL TR 4.

Clegg, F. W., ``The SPOOF: A New Technique for Analyzing the Effects of Faults on Logic Networks," CSL TR 11.

Clegg, F. W., ``Use of SPOOF's in the analysis of Faulty Logic Networks," IEEE Trans. Comput., C-22, No. 3, Mar. 1973, pp. 229-234.

Coates, C. L., et. al., ``An Undergraduate Computer Engineering Option for Electrical Engineering," (Invited Paper), Proceedings of the IEEE, Vol. 59, No. 6, pp. 854-860, June 1971.

Côrtes, M. L., and R. K. Iyer, ``Device Failures and System Activity: A Thermal Effects Model," FTC'84, pp. 71-76. (CRC TR 84-2)

Côrtes, M., and E. J. McCluskey, ``Modeling Power Supply Disturbances in Digital Circuits," ISSCC'86, pp. 164-165. (CRC TR 86-1)

Côrtes, M., E. J. McCluskey, K. D. Wagner, and D. J. Lu, ``Properties of Transient Errors due to Power-Supply Disturbances," ISCAS'86, pp. 1046-1049. (CRC TR 86-1)

Côrtes, M., and E. J. McCluskey, ``An Experiment on Intermittent-Failure Mechanisms," ITC'86, pp. 435-442. (CRC TR 86-5 and 87-7)

Côrtes, M. L., S. D. Millman, H. A. Goosen, and E. J. McCluskey, ``Techniques for Injecting Non Stuck-At Faults," CRC TR 87-21.

Dao, T. T., L. K. Russell, D. R. Preedy, and E. J. McCluskey, ``Multilevel IIL with Threshold Gates," Proc., IEEE Int. Solid-State Circuits Conf., pp. 110-112, Philadelphia, PA, Feb. 16-18, 1977.

Dao, T. T., E. J. McCluskey, and L. K. Russell, "Multivalued Integrated Injection Logic," IEEE Trans. Comput., C-26, No. 12, pp. 1233-1241, Dec. 1977.

Davies, D., and J. F. Wakerly, ``Synchronization and Matching in Redundant Systems," IEEE Trans. Comput., Vol. C-27, No. 6, pp. 531-539, June 1978.

Davies, D., ``Reliable Synchronization and Matching in Redundant Systems," CSL TR 169.

Dias, F. J. O., ``Fault Masking in Combinational Logic Circuits," IEEE Trans. Comput., Vol. C-24, No. 5, pp. 476-482, May 1975. (CSL TN 31)

Dias, F. J. O., ``Fault Masking in Combinational Circuits," FTC'74, pp. 14-19, 1974.

Dias, F. J. O., ``Truth-table Verification of an Iterative Logic Array," IEEE Trans. Comput., C-25, No. 6, pp. 605-613, June 1976. (CSL TR 94)

CSL Faculty, ``Research in the Digital Systems Laboratory," CSL TR 150.

Dong, H., and E. J. McCluskey, ``Design of Fully Testable Programmable Logic Arrays," CRC TR 81-20.

Dong, H., and E. J. McCluskey, ``Matrix Representation of PLA's and an Application to Characterizing Errors," CRC TR 81-11.

Dong, H., and E. J. McCluskey, ``Concurrent Testing of Programmable Logic Arrays," CRC TR 82-11.

Dong, H., ``Modified Berger Codes for Detection of Unidirectional Errors," FTC'82, pp. 317-320 and IEEE Trans. Comput., Vol. C-33, No. 6, pp. 572-575, June 1984. (CRC TR 81-16 and 82-3)

Dong, H., ``Modified Berger Codes for Detection of Unidirectional Errors," IEEE Trans. Comput., c-33, No. 6, pp. 572-575, June 1984. (CRC TR 81-16 and 82-3)

Ersoz, A., D. M. Andrews, and E. J. McCluskey, ``The Watchdog Task: Concurrent Error Detection Using Assertions," CRC TR 85-8.

Ferhani, F.-F. and E. J. McCluskey, ``Classifying Bad Chips and Ordering Test Sets," ITC'06.

Franco, P., N. Saxena, and E. J. McCluskey, ``Relating Aliasing in Signature Analysis to Test Length and Register Design," ISCAS'91, pp. 1889-1892. (CRC TR 91-4)

Franco, P., and E. J. McCluskey, ``Delay Testing of Digital Circuits By Output Waveform Analysis," ITC'91, pp. 798-807. (CRC TR 91-5)

Franco, P., and E. J. McCluskey, ``On-Line Delay Testing of Digital Circuits," CRC TR 93-7.

Franco, P., and E. J. McCluskey, ``On Line Delay Testing of Digital Circuits," VTS'94, pp. 167-173. (CRC TR 94-1)

Franco, P., and E. J. McCluskey, ``3-Pattern Delay Fault Tests," VTS'94, pp. 452-456. (CRC TR 94-1)

Franco, P., and E. J. McCluskey, ``WSIM: A Symbolic Waveform Simulator," CRC TR 94-4.

Franco, P., R. L. Stokes, W. D. Farwell, and E. J. McCluskey, ``An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment," CRC TR 94-5.

Franco, P., ``Testing Digital Circuits for Timing Failures by Output Waveform Analysis," CRC TR 94-9.

Franco, P., W. D. Farwell, R. L. Stokes, and E. J. McCluskey, ``An Experimental Chip to Evaluate Test Techniques Chip and Experiment Design," ITC'95, pp. 653-662.

Franco, P., S. Ma, T. Y. J. Chang, Y. Chu, S. Wattal, R. Stokes, W. Farwell, E. J. McCluskey, ``Analysis and Detection of Timing Failures in an Experimental Test Chip," ITC'96, pp. 671-700.

Freeman, G., D. Liu, B. Wooley, and E. J. McCluskey, ``Two CMOS Metastability Sensors," ITC'86, pp. 140-144. (CRC TR 86-5)

Fregni, E., and R. C. Ogus, ``Error Recovery Techniques in Computer Systems: A Survey," CSL TN 42.

Fregni, E., M. D. Beaudry, and R. C. Ogus, ``A Markov Model for Reconfigurable Computer Systems," CSL TN 43.

Fu, P. L., ``Consistency Unit for Fault-Tolerant Multiprocessor," FTC'80, pp. 363-368. (CSL TN 177)

Fu, P. L., ``Consistency in Interprocessor Communications for Fault-tolerant Multiprocessors," CRC TR 81-10.

Fukazawa, T., and E. J. McCluskey, ``Assertions for Dynamic Error Detection on a Parallel Processor," CRC TR 90-5.

Furuya, K., and E. J. McCluskey, ``Two-Pattern Test Capabilities of Autonomous TPG Circuits," ITC'91, pp. 704-711. (CRC TR 91-5)

Furuya, K., and E. J. McCluskey, ``A Method and the Effect of Shuffling Compactor Inputs in VLSI Self-Testing," Special Issue on PRFTS, Trans. on Information and Systems of IEICE, pp. 842-846, Nov. 1992.

Furuya, K., S. Seki, and E. J. McCluskey, "Synthesis of Autonomous TPG Circuits Oriented for Two-Pattern Testing," First Asian Test Symposium, Hiroshima, Japan, pp. 235-240, Nov. 26-27, 1992.

Furuya, K., and E. J. McCluskey, ``Two-Pattern Test Capabilities of Autonomous TPG Circuits," Trans. on Information and Systems of IEICE, Vol. E76-D, No. 7, pp. 800-808, July 1993.

Goosen, H. A., M. L. Côrtes, and E. J. McCluskey, ``Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques," CRC TR 87-17.

Goosen, H. A., and T. Nanya, ``The Byzantine Hardware Fault Model," CRC TR 88-3.

Hao, H., and E. J. McCluskey, ``Survey of Combinational Shifter Implementations," CRC TR 89-4.

Hao, H., and E. J. McCluskey, ``Resistive Shorts Within CMOS Gates," ITC'91, pp. 292-301. (CRC TR 91-1 and 91-5)

Hao, H., and E. J. McCluskey, ``On the Modeling and Testing of Gate Oxide Shorts in CMOS Logic Gates," 1991 IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Hidden Valley, PA, pp. 161-174, Nov. 18-20, 1991. (CRC TR 91-6)

Hao, H., and E. J. McCluskey, ``Analysis of Gate Oxide Shorts in CMOS Circuits," CRC TR 92-1.

Hao, H., and E. J. McCluskey, ``Very-Low-Voltage Testing for Weak CMOS Logic IC's," ITC'93, pp. 275-284. (CRC TR 93-1 and CRC TR 93-2)

Hao, H., and E. J. McCluskey, ``Analysis of Gate Oxide Shorts in CMOS Circuits," IEEE Trans. Comput.Vol. 42, No. 12, pp. 1510-1516, Dec. 1993.

Hassan, S. Z., ``Algebraic Analysis of Parallel Signature Analyzers," CRC TR 82-5.

Hassan, S. Z., D. J. Lu, and E. J. McCluskey, ``Parallel Signature Analyzers -- Detection Capability and Extensions," COMPCON'83, pp. 440-445. (CRC TR 82-20)

Hassan, S. Z., and E. J. McCluskey, ``Testing PLAs Using Multiple Parallel Signature Analyzers," FTC'83, pp. 422-425. (CRC TR 82-9, 83-3 and 83-13)

Hassan, S. Z., ``Signature Testing of Sequential Machines," ITC'83, pp. 714-718, and IEEE Trans. Comput., Vol. C-33, No. 8, pp. 762-764, Aug. 1984. (CRC TR 82-18 and 83-10)

Hassan, S. Z., and E. J. McCluskey, ``Increasing Effective Fault Coverage of Parallel Signature Analyzers," CRC TR 84-3.

Hassan, S. Z., and E. J. McCluskey, ``Increased Fault Coverage through Multiple Signatures," FTC'84, pp. 354-359. (CRC TR 83-17 and 84-2)

Hassan, S. Z., and E. J. McCluskey, ``Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis," ITC'84, pp. 320-326. (CRC TR 84-8)

Hassan, S. Z., and E. J. McCluskey, ``Enhancing the Effectiveness of Parallel Signature Analyzers," ICCAD'84, pp. 102-104. (CRC TR 84-10)

Hayes, J. P., and E. J. McCluskey, ``Testability Considerations in Microprocessor-Based Design," Computer, pp. 7-26, Mar. 1980. (A Reliable LZ Data Compressor on Reconfigurable Coprocessors," Symp., Field-Programmable Custom Computing Machines, pp. 249-258, Napa Valley, CA, April 16-19, 2000.)

Huang, W.-J., and E. J. McCluskey, ``Transient Errors and Rollback Recovery in LZ Compression," 2000 Pacific Rim Int. Symposium on Dependable Computing (PRDC 2000), pp. 128-135, Los Angeles, CA, Dec. 18-20, 2000.

Huang, W.-J., and E. J. McCluskey, ``A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations," Ninth ACM Int. Symp. Field-Programmable Gate Arrays (FPGA'01), pp. 183-192, Monterey, CA, Feb. 11-13, 2001.

Huang, W.-J., S. Mitra, and E. J. McCluskey, ``Fast Run-Time Fault Location in Dependable FPGAs," CRC TR 01-5, May 2001.

Hughes, J. L. A., ``A High-level Representation for Implementing Control-Flow Structures in Dataflow Programs," CRC TR 82-4.

Hughes, J. L. A., ``Implementing Control-flow Structures in Dataflow Programs," COMPCON'82, pp. 87-90.

Hughes, J. L. A., E. J. McCluskey, and D. J. Lu, ``Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs," FTC'83, pp. 169-172. (CRC TR 83-3 and 83-18)

Hughes, J. L. A., ``Error Detection and Correction Techniques for Dataflow Systems," FTC'83, pp. 318-321. (CRC TR 83-1 and 83-3)

Hughes, J. L. A., E. J. McCluskey, and D. J. Lu, ``Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs," IEEE Trans. Comput., Vol. C-33, no. 6, pp. 546-550, June 1984. (CRC TR 83-3)

Hughes, J. L. A., and E. J. McCluskey, ``An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-At Fault Test Sets," ITC'84, pp. 52-58. (CRC TR 84-8)

Hughes, J. L. A., S. Mourad, and E. J. McCluskey, ``An Experimental Study Comparing 74LS181 Test Sets," COMPCON'85, pp. 384-387. (CRC TR 84-13)

Hughes, J. L. A., and E. J. McCluskey, ``Multiple Stuck-at Fault Coverage of Single Stuck-at Fault Test Sets," ITC'86, pp. 368-374. (CRC TR 86-5)

Ishizuka, O., ``Application of Multi-valued Multi-threshold Network for Realizing Unary Functions," CRC TR 81-4.

Ichikawa, M., ``Constant Weight Code Generators," CRC TR 82-7.

Iyer, R. K., ``On the Employment of Variance for Reliability Modeling of Fault Tolerant Systems," FTC'79, pp. 63-66.

Iyer, R. K., ``A Study of the Effect of Uncertainty in Failure Rate Prediction on System Reliability," FTC'80, pp. 219-224. (CSL TN 177)

Iyer, R. K., S. E. Butner, and E. J. McCluskey, ``An Exponential Failure/Load Relationship: Results of a Multi-computer Statistical Study," CRC TR 81-6.

Iyer, R. K., and D. J. Rossetti, ``A Statistical Load Dependency Model for CPU Errors at SLAC," FTC'82, pp. 363-372. (CRC TR 81-19 and 82-3)

Iyer, R. K., S.E. Butner, and E. J. McCluskey, ``A Statistical Failure/Load Relationship: Results of a Multicomputer Study," IEEE Trans. Comput., Vol. C-31, No. 7, pp. 697-706, July 1982.

Iyer, R. K., and H. H. Amer, ``Effect of Uncertainty in Failure Rate on Memory System Reliability," CRC TR 83-9.

Iyer, R. K., and D. J. Rossetti, ``Hard CPU Related Failures and System Activity: Measurement and Modelling," CRC TR 83-6.

Iyer, R. K., and D. J. Rossetti, ``Permanent CPU Errors and System Activity: Measurement and Modelling," Proc., Real-time Systems Symposium, Arlington, VA, pp. 61-72, Dec. 6-8, 1983. (CRC TR 83-11)

Iyer, R. K., ``Reliability Evaluation of Fault-Tolerant Systems - Effect of Variability in Failure Rates," IEEE Trans. Comput., Vol. C-33, No. 2, pp. 197-200, Feb. 1984.

Iyer, R. K., and P. Velardi, ``A Statistical Study of Hardware-Related Software Errors in MVS," FTC'84, pp. 192-197. (CRC TR 83-12 and 84-2)

Iyer, R. K., and D. J. Rossetti, ``Measurement and Modeling of Computer Reliability as Affected by System Activity," CRC TR 85-21.

Iyer, R. K., and D. J. Rossetti, ``Effect of System Workload on Operating System Reliability: A Study on IBM 3081," IEEE Trans. Software Engineering, Vol. SE-11, No. 12, pp. 1438-1448, Dec. 1985.

Iyer, R. K., and P. Velardi, ``Hardware-Related Software Errors: Measurement and Analysis," IEEE Trans. Software Engineering, Vol. SE-11, No. 2, pp. 223-230, Feb. 1985.

Iyer, R. K., and Rossetti, D. J., ``A Measurement-Based Model for Workload Dependence of CPU Errors," IEEE Trans. Comput., Vol. C-35, No. 6, pp. 511-519, June 1986.

Khakbaz, J., ``A Novel Totally-self-checking 1-out-of-n Checker," CRC TR 81-12.

Khakbaz, J., and E. J. McCluskey, ``Self-testing Embedded Parity Checkers -- Exhaustive XOR Gate Testing," CRC TR 82-10.

Khakbaz, J., and E. J. McCluskey, ``Concurrent Error Detection and Testing for Large PLA's," Joint Special Issue on VLSI, IEEE Trans. on Electron Devices, pp. 756-764 and IEEE J. of Solid-State Circuits, pp. 386-394, Apr. 1982. (CRC TR 81-14)

Khakbaz, J., ``Self-Testing Embedded Parity Trees," FTC'82, pp. 109-116. (CRC TR 82-3)

Khakbaz, J., ``Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes," IEEE Trans. Comput., Vol. C-31, pp. 677-681, July 1982.

Khakbaz, J., and E. J. McCluskey, ``Self-Testing Embedded Code Checkers," COMPCON'83, pp. 452-457. (CRC TR 82-20 and 83-19)

Khakbaz, J., ``A Testable PLA Design with Low Overhead and High Fault Coverage," FTC'83, pp. 426-429, and IEEE Trans. Comput., Vol. C-33, No. 8, pp. 743-745, Aug. 1984. (CRC TR 82-17 and 83-3)

Khakbaz, J., and E. J. McCluskey, ``Self-testing Embedded Parity Checkers," IEEE Trans. Comput., Vol. C-33, No. 8, pp. 753-756, Aug. 1984.

Khakbaz, J., and E. J. McCluskey, ``Concurrent Error Detection and Testing for Large PLA's," DIGITAL VLSI SYSTEMS, M. I. Elmasry, ed., pp. 494-502, IEEE Press, New York, 1985. (Reprinted from IEEE Trans. Electron Devices, Vol. ED-29, Apr. 1982, pp. 756-764.) (CRC TR 81-14)

Khakbaz, J., and S. Bozorgui-Nesbat, ``Minimizing Extra Hardware for Fully Testable PLA Design," Proc., IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 102-104, Nov. 18-21, 1985.

Kiryukhin, V. V., and A.M . Chernykh, ``A Quadruple-Computer Redundant Type Fault-Tolerant System," USA-Japan'78, pp. 374-377.

Khodadad-Mostashiry, B., ``Break Fault in Circuits with Parity Prediction," CSL TN 183.

Khodadad-Mostashiry, B., ``Parity Prediction in Combinational Circuits," FTC'79, pp. 185-188. (CSL TN 151)

Kolupaev, S. G., ``Separate Non-Homomorphic Checking Codes for Binary Addition," CSL TR 35.

Kolupaev, S. G., ``Self-Testing Residue Trees," CSL TR 49.

Kolupaev, S., ``Cascade structure in self-checking networks," FTC'77, pp. 150-154. (CSL TR 108)

Lau, C., C. M. Hu, and E. J. McCluskey, ``Research in Advanced Electronic System Reliability," Naval Research Reviews, Vol. XLI, pp. 9-19, Three/1989.

Lee, D. and E. J. McCluskey, ``Experimental Data on Yield Loss," SRC Annual Report, Dec. 2004.

Lee, D. and E. J. McCluskey, ``Experimental Data on Test Escapes," SRC Annual Report, Dec. 2004.

Lee, D. and E. J. McCluskey, ``Techniques to Identify the Potential Cause of Overkill," SRC Annual Report, Jun. 2005.

Lee, D. and E. J. McCluskey, ``Comparisons of Various Scan Delay test Techniques," SRC Annual Report, Dec. 2005.

Lee, D., E. Volkerink and I. Park and J. Rearick, ``Empirical Validation of Yield Recovery Using Idle-Cycle Insertion," IEEE Design and Test of Computers, vol 24, issue 4, July-Aug 2007, pp. 362--372.

Lee, J., I. Park, and E. J. McCluskey, ``Error Sequence Analysis," VTS'08, pp. 255-260.

Li, J. C.-M., and E. J. McCluskey, ``IDDQ Data Analysis Using Current Signature," 1998 IEEE Int. Workshop on IDDQ Testing, pp. 37-42, San Jose, CA, Nov. 12-14, 1998.

Li, J. C.-M., J. T.-Y. Chang, C. W. Tseng, and E. J. McCluskey, ``ELF35 Experiment - Chip and Experiment Design," CRC TR 99-3, Oct. 1999.

Li, J. C.-M., and E. J. McCluskey, ``Testing for Tunneling Opens," ITC'00, pp. 85-94.

Li, J. C.-M., and E. J. McCluskey, ``Diagnosis of Tunneling Opens," VTS'01, pp. 22-27. Los Angeles, CA, Apr. 29-May 3, 2001. Liu, D., and E. J. McCluskey, ``Design of CMOS VLSI Circuits for Testability," Proc., IEEE Custom Integrated Circuits Conferenc (CICC'86), pp. 421-424, and Journ. Semicustom IC's, Vol. 4, No. 4, pp. 5-10, June 1987. (CRC TR 86-1) Proceedings of IEEE Custom Integrated Circuits Conferenc Liu, D. L., and E. J. McCluskey, ``CMOS Scan-Path IC Design for Stuck-Open Fault Testability," IEEE Journ. Solid State Circuits, Vol. SC-22, No. 5, pp. 880-85, Oct. 1987. (CRC TR 87-10)

Liu, D. L., and E. J. McCluskey, ``A VLSI CMOS Circuit Design Technique to Aid Test Generation," Proc., 1987 Phoenix Conf. Comput. and Comm., Scottsdale, AZ, pp. 116-120, Feb., 1987. (CRC TR 86-18)

Liu, D. L., and E. J. McCluskey, ``A CMOS PLA Design for Built-In Self-Test," ISCAS'87, pp. 859-862. (CRC TR 87-5)

Liu, D. L., and E. J. McCluskey, ``High Fault Coverage Self-Test Structures for CMOS ICs," Proc., 1987 IEEE Custom Integrated Circuits Conf., Portland, OR, pp. 68-71, May 1987. (CRC TR 87-5)

Liu, D. L., and E. J. McCluskey, ``Design of Large Embedded CMOS PLA for Built-In Self-Test," ICCD'87, pp. 678-681.

Liu, D. L., and E. J. McCluskey, ``A CMOS Cell Library Design for Testability," VLSI Systems Design, pp. 58-65, May 1987.

Liu, D. L., and E. J. McCluskey, ``Designing CMOS Combinational Circuits for Switch-level Testability," IEEE Design & Test of Comput., pp. 42-49, Aug. 1987. (CRC TR 87-9)

Liu, D. L., ``Testable Structures for CMOS VLSI Circuits," CRC TR 87-15.

Liu, D. L., and E. J. McCluskey, ``Design of Large Embedded CMOS PLA's for Built-In Self-Test," IEEE Trans. CAD, Vol. 7, No. 1, pp. 50-59, Jan. 1988.

Losq, J., ``Redundancy Scheme for Optimum Multiple Fault Tolerance," CSL TN 33.

Losq, J., ``Computer Networks with Constant Maximum Delay Under Communication Line Failures," CSL TN 34.

Losq, J., ``Modeling and Reliability of Redundant Digital Systems," CSL TR 58.

Losq, J., ``Influence of Fault-detection and Switching Mechanisms on the Reliability of Stand-by Systems," FTC'75,pp. 81-86. (CSL TR 75)

Losq, J., ``Multiple Failures and Redundant Systems," Digest of 1976 Johns Hopkins Conf. on Information Sciences and Systems, pp. 52-57, Baltimore, MD, Apr. 1976.

Losq, J., ``Referenceless random testing," FTC'76, pp. 108-113.

Losq, J., "A Highly Efficient Redundancy Scheme: Self-purging Redundancy," IEEE Trans. Comput., C-25, No. 6, pp. 269-278, June 1976. (CSL TR 62)

Losq, J., ``Effects of Failures on Performance of Gracefully Degradable Systems," CSL TN 103.

Losq, J., ``Effects of Failures on Gracefully Degradable Systems," FTC'77, pp. 29-34.

Losq, J., ``Efficiency of Compact Testing for Sequential Circuits," FTC'77, pp. 168-174. (CSL TN 104)

Losq, J., ``Enumeration of the Critical Fault Patterns in Fault-Tolerant Computer Systems," FTC'78, pp. 31-36. (CSL TN 128)

Losq, J., ``Fault-Tolerant Communication Networks for Computer Networks," FTC'78, p. 204. (CSL TN 127)

Losq, J., ``Efficiency of Random Compact Testing," IEEE Trans. Comput., Vol. C-27, No. 6, pp. 516-525, June 1978.

Losq, J., ``Testing for Intermittent Failures in Combinational Circuits," USA-Japan'78, pp. 165-170.

Lu, D. J., ``Quantitative Comparison of Self-Checking Circuit Designs," CSL TN 130.

Lu, D. J., ``Structural Integrity Checking," CSL TN 149.

Lu, D. J., ``Quantitative Comparison of Self-checking Circuit Designs: Definitions and an Example for Linear Feedback Shift Registers," FTC'78, p. 221.

Lu, D. J., ``Self-Checking Linear Feedback Shift Registers," FTC'80, pp. 269-271. (CSL TN 177)

Lu, D. J., ``Watchdog Processors and VLSI," Proc., 1980 National Electronics Conf., pp. 240-245, Chicago, IL, Oct. 27-28, 1980. (CSL TN 179)

Lu, D. J., E. J. McCluskey, and M. Namjoo, "Summary of Structural Integrity Checking," Proc., Distributed Data Acquisition, Computing, and Control Symposium, pp. 107-109, Miami Beach, FL, Dec. 3-5, 1980. (CSL TN 181)

Lu, D. J., ``Quantitative Measures and Figures of Merit for Self-checking Circuits," CRC TR 81-8.

Lu, D. J., ``Testing VHSIC Devices," CRC TR 82-15.

Lu, D. J., and E. J. McCluskey, ``Recurrent Test Patterns," ITC'83, pp. 76-82. (CRC TR 83-10)

Lu, D. J., and E. J. McCluskey, ``Quantitative Evaluation of Self-Checking Circuits," IEEE Trans. Computer-Aided Design, No. 2, pp. 150-155, Apr. 1984.

Lu, D. J., ``Watchdog Processors and Structural Integrity Checking," Reliable Distributed System Software, J. A. Stankovic, ed., pp. 208-212, IEEE Computer Society Press, Silver Spring, Maryland, 1985. (Reprinted from IEEE Trans. Comput., Vol. C-31, No. 7, pp. 681-685, July 1982.) (CRC TR 81-5)

Ma, S. C., and E. J. McCluskey, ``Non-Conventional Faults in BiCMOS Digital Circuits," ITC'92, pp. 882-891. (CRC TR 92-2)

Ma, S. C., and E. J. McCluskey, ``Open Faults in BiCMOS Gates," VTS'94, pp. 434-439. (CRC TR 93-4 and CRC TR 94-1)

Ma, S. C., and E. J. McCluskey, ``Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic," CRC TR 94-13.

Ma, S. C., and E. J. McCluskey, ``Open Faults in BiCMOS Gates," ICCAD'95, pp. 567-575, May 1995.

Ma, S. C., ``Testing BiCMOS and Dynamic CMOS Logic," CRC TR 95-1.

Ma, S. C., P. Franco, and E. J. McCluskey, ``An Experimental Chip to Evaluate Test Techniques Experiment Results," ITC'95, pp. 663-672.

Mahmood, A., E. J. McCluskey, and D. J. Lu, ``Concurrent Fault Detection Using a Watchdog Processor and Assertions," ITC'83, pp. 622-628. (CRC TR 83-10 and 83-16)

Mahmood, A., D. M. Andrews, and E. J. McCluskey, ``Writing Executable Assertions to Test Flight Software," Eighteenth Annual Asilomar Conference on Circuits, Systems, and Computers, Pacific Grove, CA, pp. 262-266, Nov. 5-7, 1984. (CRC TR 84-14)

Mahmood, A., D. M. Andrews, and E. J. McCluskey, ``Executable Assertions and Flight Software," DASC'84, pp. 346-351. (CRC TR 84-11 and 84-16)

Mahmood, A., and E. J. McCluskey, ``Watchdog Processors: Error Coverage and Overhead," FTC'85, pp. 214-219. (CRC TR 84-15 and 85-3)

Mahmood, A., A. Ersoz, and E. J. McCluskey, "Concurrent System-Level Error Detection Using a Watchdog Processor," ITC'85, pp. 145-152. (CRC TR 85-11)

Mahmood, A., and E. J. McCluskey, ``Concurrent Error Detection Using Watchdog Processors - A Survey," IEEE Trans. Comput., Vol. 37, No. 2, pp. 160-174, Feb. 1988. (CRC TR 85-7)

Makar, S. R., and E. J. McCluskey, ``On The Testing Of Multiplexers," ITC'88 , pp. 669-679. (CRC TR 88-5)

Makar, S., and E. J. McCluskey, ``The Critical Path for Multiple Faults," ICCAD'89, pp. 162-165, Nov. 6-9, 1989. (CRC TR 89-3)

Makar, S. R., and E. J. McCluskey, ``Minimal Single Stuck-at Tests For Multiplexers," CRC TR 90-3.

Makar, S. R., and E. J. McCluskey, ``Implementing Fault Models in Verilog," CRC TR 90-7.

Makar, S., and E. J. McCluskey, ``Using Checking Experiments To Test D-Latches" CRC TR 94-11.

Makar, S., and E. J. McCluskey, ``Checking Experiments to Test Latches," VTS'95, pp. 196-201.

Makar, S. R., and E. J. McCluskey, ``Functional Tests for Scan Chain Latches," ITC'95, pp. 606-615.

Makar, S. R., and E. J. McCluskey, ``Some Faults Need an Iddq Test," 1996 IEEE Int. Workshop on IDDQ Testing, pp. 102-103, Washington, DC, Oct. 24-25, 1996. (CRC TN 96-1)

Makar, S. R., and E. J. McCluskey, ``ATPG For Scan Chain Latches and Flip-Flops," VTS'97, pp. 364-369. (CRC TN 96-3)

Makar, S. R., and E. J. McCluskey, ``IDDQ Test Pattern Generation for Scan Chain Latches and Flip-Flops," 1997 Int. Workshop on IDDQ Testing, pp. 2-6, Washington, DC, Nov. 5-6, 1997.

Marhoefer, M., and E. J. McCluskey, ``An Experimental Study of Supergates," CRC TR 88-6.

Martinolle, F., ``Fusion of VHDL Processes," CRC TR 91-7.

Matarai, H., and E. J. McCluskey, ``Design of a Parallel Encoder/Decoder for the Hamming Code Using ROM," CSL TR 36.

McCluskey, D., ``Bibliography of the 1986 CRC Publications," CRC TR 87-0.

McCluskey, E. J., ``Minimization of Boolean Functions," Bell System Tech. J., Vol. 35, no. 5, pp. 1417-1444, Nov., 1956 and Computer Design Development, E.E. Swartzlander, Ed., Hayden Book Co., Inc., New Jersey, pp. 37-78, 1976.

McCluskey, E. J., and F. W. Clegg, ``Fault Equivalence in Combinational Logic Networks," IEEE Trans. Comput., C-20, No. 11, Nov. 1971, pp. 1286-1293. (CSL TN 10)

McCluskey, E. J., ``Probability Models for Logic Networks," Proc., Fourth Manitoba Conference on Numerical Math, University of Manitoba, Winnipeg, Canada, pp. 21-28, Oct. 2-5, 1974.

McCluskey, E. J., ``Micros, Minis, and Networks," Proc., Meeting on 20 Years of Computer Science, (CALCOLO, Supplemento N.1 - Vol. XII, Istitudo di Elaborazione della Informazione del CNR), Pisa, Italy, pp. 23-33, June 16-19, 1975. (CSL TN 58)

McCluskey, E. J., J. F. Wakerly, and R. C. Ogus, ``Center for Reliable Computing: Current Research," CSL TR 100.

McCluskey, E. J., and R. C. Ogus, ``Survey of Computer Reliability Studies," Electro-Technology, pp. 82-95, Dec. 1975.

McCluskey, E. J., ``A Survey of Research at the Center for Reliable Computing, Stanford University," Journ. Design Automation and Fault-Tolerant Computing, Vol. 1, No. 1, pp. 85-90, Oct. 1976. (CSL TN 96)

McCluskey, E. J., and R. C. Ogus, ``Comparative Architecture of High Availability Computer Systems," COMPCON'77, pp. 289-293. (CSL TN 107)

McCluskey, E. J., ``Editorial," Digital Processes, Vol. 3, No. 3, pp. 187-188, Autumn 1977.

McCluskey, E. J., ``Reliability and Computer Architecture," CSL TN 122.

McCluskey, E. J., K. P. Parker, and J. J. Shedletsky, ``Boolean Network Probabilities and Network Design," IEEE Trans. Comput., Vol. C-27, No. 2, pp. 187-189, Feb. l978. (CSL TN 60)

McCluskey, E. J., ``Logic Design of Multi-Valued IIL Logic Circuits," Proc., Eight Int. Symposium on Multiple-valued Logic, Chicago, IL, pp. 14-22, May 24-26, 1978, and IEEE Trans. Comput., Vol. C-28, No. 8, pp. 546-559, Aug. 1979.

McCluskey, E. J., ``Design for Maintainability and Testability," Proc., Government Microcircuit Applications Conference, pp. 44-47, Monterey, CA, Nov. 14-16, 1978. (CSL TN 145)

McCluskey, E. J., ``Logic Design of Multi-Input Quad IIL Circuits," Proc., Ninth Int. Symposium on Multiple-Valued Logic, pp. 121-127, Bath, England, May 29-31, 1979.

McCluskey, E. J., ``Testing and Diagnosis of Logic," Proc., Euro/IFIP 79, pp. 735-738, London, England, Sep. 25-28, 1979.

McCluskey, E. J., ``Designing with PLA's," Thirteenth Asilomar Conf. on Circuits, Systems and Computers, pp. 442-445, Pacific Grove, CA, Nov. 5-7, 1979. (CSL TN 168)

McCluskey, E. J., ``Logic Design of MOS Ternary Logic," Proc., Tenth Annual Int. Symposium on Multiple-Valued Logic, pp. 1-5, Evanston, IL, June 3-5, 1980.

McCluskey, E. J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," ITC'80, pp. 11-13. (CRC TR 81-1) (CSL TN 180)

McCluskey, E. J., ``Reliable Computing Systems" Proc., Int. Computer Symposium 1980, pp. 714-723, Taipei, Republic of China, Dec. 16-18, 1980. (CSL TN 182)

McCluskey, E. J., ``Testing Digital Circuits and Systems," CSL TN 166.

McCluskey, E. J., ``Fault-tolerant Computing Systems," CSL TN 170.

McCluskey, E. J., and Hayes, J. P., ``Testability Considerations in Microprocessor-Based Design," Tutorial: Microcomputer System Software and Languages, Belton E. Allen, editor, 1980 IEEE Catalog No. EHO 174-3, Library of Congress No. 80-84352.

McCluskey, E. J., ``Testing VHSIC Devices," CRC TR 81-3.

McCluskey, E. J., and J. F. Wakerly, ``A Circuit For Detecting and Analyzing Temporary Failures," COMPCON'81, pp. 317-321. (CSL TN 178)

McCluskey, E. J., and S. Bozorgui-Nesbat, ``Design for Autonomous Test," IEEE Trans. Comput., pp. 866-875, Nov. 1981.

McCluskey, E. J., ``A Discussion of Multiple-valued Logic Circuits," CRC TR 82-2.

McCluskey, E. J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," Tutorial, VLSI, COMPCON'82, pp. 290-296. (CRC TR 81-1)

McCluskey, E. J., ``Fault Tolerant Systems," Journal, Information Processing Society in Japan, Vol. 23, No. 4, pp. 378-385, Apr. 1982. (CRC TR 82-1)

McCluskey, E. J., ``A Discussion of Multiple-Valued Logic Circuits," Proc., 12th Int. Symposium on Multiple-Valued Logic, Paris, France, pp. 200-205, May 25-27, 1982.

McCluskey, E. J., ``Verification Testing," DAC'82, pp. 495-500. (CRC TR 81-7)

McCluskey, E. J., ``Test Questions," (Keynote Address), FTC'82, p. 43. (CRC TR 82-3)

McCluskey, E. J., ``Built-in Verification Test," ITC'82, pp. 183-190. (CRC TR 82-12)

McCluskey, E. J., ``Design for Testability Survey," Proc., Bias Microelettronica, Sec. 4, pp. 1-9, Milan, Italy, Feb. 23-25, 1983.

McCluskey, E. J., ``Exhaustive and Pseudo-exhaustive Test," Built-in Test--Concepts and Techniques, Tutorial, ITC'83. (CRC TR 83-15)

McCluskey, E. J., ``Teaching Testing," ITC'83, pp. 163-167. (CRC TR 83-10)

McCluskey, E. J., ``Logic Design," in Encyclopedia of Computer Science and Engineering, A. Ralston & E.D. Reilly, Jr., Eds., Van Nostrand Reinhold Co., New York, NY, pp. 879-882, 1983.

McCluskey, E. J., D. J. Lu, S. Bozorgui-Nesbat, and A. Mahmood, ``Testing VHSIC Devices," CRC TR 84-1.

McCluskey, E. J., ``Pseudo-Exhaustive Testing for VLSI Devices" ATE Silicon Valley Conf., San Mateo, CA, pp. IV-5-IV-21, Apr. 10-12, 1984. (CRC TR 84-6)

McCluskey, E. J., ``Verification Testing-A Pseudoexhaustive Test Technique," IEEE Trans. Comput., Vol. C-33, No. 6, pp. 541-546, June 1984. (CRC TR 83-8)

McCluskey, E. J., ``VLSI Design for Testability," 1984 Symposium on VLSI Technology, San Diego, CA, pp. 2-5, Sep. 10-12, 1984; DASC'84, pp. 523-530 (CRC TR 84-4 and 84-11)

McCluskey, E. J., ``Errors in Education," Panel Statement, Academic Curriculum Forum, ITC'84, p. 3. (CRC TR 84-8)

McCluskey, E. J., ``Built-In Self Test Architectures," Academic Curriculum Forum, ITC'84, pp. 4-6. (CRC TR 84-8)

McCluskey, E. J., ``Testing Semi-Custom Logic," Wescon'84, Anaheim, CA, paper 31/4, Oct. 30-Nov. 2, 1984. (CRC TR 84-9)

McCluskey, E. J., ``A Survey of Design for Testability Scan Techniques," VLSI Design, Vol. V, No. 12, pp. 38-61, Dec. 1984.

McCluskey, J., ``Bibliography of 1976-1984 CRC Publications," CRC TR 85-0.

McCluskey, E. J., ``Design for Testability Reprints," CRC TR 85-6.

McCluskey, E. J., ``A Comparison of Test Pattern Generation Techniques," CRC TR 85-16.

McCluskey, E. J., ``Synchronous Digital Logic," HICSS'85, Vol. 1, pp. 52-63. (CRC TR 84-12)

McCluskey, E. J., ``Hardware Fault Tolerance," COMPCON'85, pp. 260-263. (CRC TR 84-13)

McCluskey, E. J., ``Testable IC Design," Proc., Automated Design and Engineering for Electronics Conf. (ADEE'85), pp. 252-260, Anaheim, CA, Feb. 26-28, 1985. (CRC TR 85-2)

McCluskey, E. J., ``Built-In Self-Test Techniques," IEEE Design & Test of Computers, pp. 21-28, Apr. 1985.

McCluskey, E. J., ``Built-In Self-Test Structures," IEEE Design & Test of Computers, pp. 29-36, Apr. 1985.

McCluskey, E. J., ``Testing Semi-Custom Logic," Semiconductor Int., pp. 118-123, Sep. 1985.

McCluskey, E. J., ``Test Teaching," ITC'85, pp. 235. (CRC TR 85-11)

McCluskey, E. J., ``Logic Design," Reference Data for Engineers: Radio, Electronics, Computer, and Communications, Seventh Ed., Chapter 43, Howard W. Sams & Co., Inc., Indianapolis, 1985.

McCluskey, E. J., ``A Comparison of Test Pattern Generation Techniques,"Proc. of Fault-Tolerant Systems and Diagnostics, pp. 11-20, Brno, Czechoslovakia, June 1986.

McCluskey, E. J., ``Hardware Fault Tolerance," Sixteenth Annual Institute in Computer Science, University of California at Santa Cruz, Aug. 25, 1986. (CRC TR 86-11)

McCluskey, E. J., ``Testing Futures," Test Technology Workshop, Washington, D.C., Sep. 11, 1986. (CRC TR 86-12)

McCluskey, E. J., ``VLSI Technology Research at Stanford," 20th IBM Computer Science Symposium, Japan, Oct. 10-12, 1986. (CRC TR 86-13)

McCluskey, E. J., ``Reliable Digital Systems and Related Stanford University Research," in "Dependable Computing and Fault-Tolerant Systems," Vol. 1, ``The Evolution of Fault-Tolerant Computing," Proc. of a 1-Day-Symposium in the honor of William C. Carter, A. Avizienis, H. Kopetz, and J.C. Laprie, eds., Springer-Verlag Wien, New York, pp. 215-250, 1986.

McCluskey, E. J., and S. Mourad, ``Comparing Causes of IC Failures," Perspectives in Computing, Vol. 18, Developments in Integrated Circuit Testing, D. M. Miller, ed., Academic Press Limited, pp. 13-46, 1987. (CRC TR 86-2)

McCluskey, E. J., ``Computer Society has it Backwards," IEEE Design and Test, pp. 6-7, Feb. 1987.

McCluskey, E. J., ``Short Pseudorandom Test Sequences," CRC TR 87-6.

McCluskey, E. J., ``Comparing Causes of System Failure," Microprocessing and Microprogramming 18, North-Holland, pp. 11-22, 1987.

McCluskey, E. J., S. Mourad, and K. D. Wagner, ``Probability Models for Pseudorandom Test Sequences," ITC'87, pp. 471-479. (CRC TR 87-12)

McCluskey, E. J., ``Exhaustive and Pseudo-Exhaustive Testing," CRC TR 87-13.

McCluskey, E. J., ``Reliable Digital Systems and Related Stanford University Research," The Evolution of Fault-Tolerant Computing, Springer-Verlag Wien, Austria, pp. 215-250, 1987.

McCluskey, E. J., S. Makar, S. Mourad, and K. D. Wagner, ``Probability Models for Pseudorandom Test Sequences," IEEE Trans. CAD, Vol. 7, No. 1, pp. 68-74, Jan. 1988.

McCluskey, E. J., ``Design Techniques for Testable Embedded Error Checkers," CRC TR 88-4.

McCluskey, E. J., and F. Buelow, ``IC Quality and Test Transparency," ITC'88, pp. 295-301, and IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, pp. 197-202, May 1989. (CRC TR 88-5)

McCluskey, E. J., ``Practice and Theory," ITC'88, pp. 203-204. (CRC TR 88-5)

McCluskey, E. J., ``Half a century of Logic Synthesis," EURO ASIC 90, Paris, France, May 29-31, 1990, and in Logic and Architecture Synthesis, pp. 3-8, P. Michel and G. Saucier, ed. North-Holland, 1991. (CRC TR 90-4)

McCluskey, E. J., ``Design Techniques for Testable Embedded Error Checkers," Special Issue on Fault-Tolerant Systems, Computer, pp. 84-88, July 1990.

McCluskey, E. J., ``Design for Test Overview," Microelectronic System Education Conference & Exposition, San Jose, CA, July 29-Aug. 1, 1990.

McCluskey, E. J., ``Foreword" in Structured Logic Testing, Prentice-Hall Inc., Englewood Cliffs, NJ, 1990.

McCluskey, E. J., ``Who Needs Design for Testability?," Dig. 1991 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 13-15, 1991. (CRC TR 90-8)

McCluskey, E. J., ``Techniques for Test Output Response Analysis," ISCAS'91, pp. 1869-1872. (CRC TR 91-4)

McCluskey, E. J., ``Quality and Single-Stuck Faults," ITC'93, p. 597. (CRC TR 93-2)

McCluskey, E. J., ``Logic Design," in Reference Data for Engineers: Radio, Electronics, Computer, and Communications, 8th Ed., Chapter 43, Van Valkenburg, ed., Howard W. Sams & Co., Inc., Indianapolis, 1993.

McCluskey, E. J., ``Logic Design," in Encyclopedia of Computer Science and Engineering, 3rd Ed., Anthony Ralston and Edwin D. Reilly, eds., Van Nostrand Reinhold, New York, pp. 775-778, 1993.

McCluskey, E. J., ``Switching Theory," in Encyclopedia of Computer Science and Engineering, 3rd Ed., Anthony Ralston and Edwin D. Reilly, eds., Van Nostrand Reinhold, New York, pp. 1332-1336, 1993.

McCluskey, E. J., ``Logic Design," in Encyclopedia of Computer Science and Engineering, 4th Ed. Anthony Ralston, Edwin D. Reilly, and David Hemmendinger, Eds, Grove's Dictionary, Inc., New York, pp. 1014-1016, 2000.

McCluskey, E. J., ``Switching Theory," in Encyclopedia of Computer Science and Engineering, 4th Ed. Anthony Ralston, Edwin D. Reilly, and David Hemmendinger, Eds, Grove's Dictionary, Inc., New York, pp. 1727-1731, 2000.

McCluskey, E. J., and C.-W. Tseng, ``Stuck-Fault Tests vs. Actual Defects," ITC'00, pp. 336-343.

McCluskey, E. J., ``Why Defects Escape some of our Tests," ITC'00, p. 1125.

McCluskey, E. J., A. A. Al-Yamani, C.-M. Li, C.W. Tseng, E. Volkerink, F. Ferhani, E. Li, and S. Mitra,``ELF-Murphy Data on Defects and Test Sets," VTS'04.

McCluskey, E. J., et. al.,``CRC Publications in VLSI Test Symposium 2004," CRC TR 04-02.

Mei, K. C. Y., ``Fault Dominance in Combinational Circuits," CSL TN 2.

Mei, K. C. Y., ``Bridging and Stuck-at Faults," IEEE Trans. Comput., C-23, No. 7, July 1974, pp. 720-727.

Miller, D. H., ``A Taxonomy of Fault-Tolerant Techniques," CSL TN 175.

Millman, S. D., ``Using LASAR for CMOS Bridging Fault Simulation," CRC TR 88-2.

Millman, S. D., and E. J. McCluskey, ``Detecting Bridging Faults With Stuck-at Test Sets," ITC'88, pp. 773-783. (CRC TR 87-20 and 88-5)

Millman, S. D., and E. J. McCluskey, ``Detecting Stuck-Open Faults with Stuck-At Test Sets," IEEE Custom Integrated Circuits Conference, San Diego, CA, May 15-18, 1989. (CRC TR 89-2 and 89-5)

Millman, S. D., and E. J. McCluskey, ``Pseudorandom Test for Bridging Faults," CRC TR 89-7.

Millman, S. D., J. M. Acken, and E. J. McCluskey, ``Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries," CRC TR 89-8.

Millman, S., ``Nonclassical Faults in CMOS Digital Integrated Circuits," CRC TR 89-9.

Millman, S. D., E. J. McCluskey, and J. M. Acken, ``Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries," ITC'90, pp. 860-870.

Millman, S., and E. J. McCluskey, ``Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers," FTC'91, pp. 154-161. (CRC TR 89-6 and 91-5)

Min, Y., ``Generating a Complete Test for Programmable Logic Arrays (PLAs)," CRC TR 83-4.

Min, Y., ``A Unified Fault Model for Programmable Logic Arrays," CRC TR 83-5.

Mitarai, H., and E. J. McCluskey, ``Design of a Parallel Encoder/Decoder for the Hamming Code, Using ROM," CSL TR 72-36.

Mitra, S., L. Avra, and E. J. McCluskey, ``Scan Synthesis for One-Hot Signals," 4th IEEE Intl. Test Synthesis Workshop, Santa Barbara, CA, May 5-7, 1997.

Mitra, S., L. Avra, and E. J. McCluskey, ``Scan Synthesis for One-Hot Signals," ITC'87, pp. 714-722.

Mitra, S., L. Avra, and E. J. McCluskey, ``An Output Encoding problem and a Solution Technique," ICCAD'97, pp. 304-307. (CRC TR 97-1 and 99-1)

Mitra, S., and E. J. McCluskey, ``Output Encoding for Hazard-Free Robust Path Delay Fault Testability," Fifth IEEE Intl. Test Synthesis Workshop, Santa Barbara, CA, Mar. 9-11, 1998.

Mitra, S., P. P. Shirvani, and E. J. McCluskey, ``Fault Location in FPGA-Based Reconfigurable Systems," IEEE Intl. High Level Design Validation and Test Workshop, La Jolla, CA, Nov. 12-14, 1998.

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``Design Diversity for Redundant Systems," FTC'99, Fast Abstracts, pp. 33-34.

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``A Design Diversity Metric and Reliability Analysis for Redundant Systems," ITC'99, pp. 662-671. (CRC TR 99-4)

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``Non-Self-Testable Faults in Duplex Systems," IEEE High Level Design and Validation Test Workshop (HLDVT'99), pp. 102-109, San Diego, CA, Nov. 4-6, 1999.

Mitra, S., and E. J. McCluskey, ``Design of Redundant Systems Protected Against Common-Mode Failures," CRC TR 00-2, Feb. 2000.

Mitra, S., L. J. Avra, and E. J. McCluskey, ``Efficient Multiplexer Synthesis," CRC TR 00-3, Mar. 2000.

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``Fault Escapes in Duplex Systems," VTS'00, pp. 453-458. (CRC TR 00-1)

Mitra, S., and E. J. McCluskey, ``Word-Voter: A New Voter Design for Triple Modular Redundant Systems," VTS'00, pp. 465-470.

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``Common-Mode Failures in Redundant VLSI Systems: A Survey," IEEE Trans. on Reliability, Vol. 49, No. 3, pp. 285-295, Sep. 2000.

Mitra, S., L. J. Avra, and E. J. McCluskey, ``Efficient Multiplexer Synthesis Techniques," IEEE Design and Test of Computers, Vol. 17, No. 4, pp. 90-97, Oct.-Dec. 2000.

Mitra, S., and E. J. McCluskey, ``Combinational Logic Synthesis for Diversity in Duplex Systems," ITC'00, pp. 179-188.

Mitra, S., and E. J. McCluskey, ``Which Concurrent Error Detection Scheme to Choose?," ITC'00, pp. 985-994.

Mitra, S., W.-J. Huang, N. R. Saxena, S.-Y. Yu, and E. J. McCluskey, ``Dependable Adaptive Computing Systems, The Stanford CRC ROAR Project," 2000 Pacific Rim Int. Symposium on Dependable Computing (PRDC 2000), Fast Abstracts, pp. 15-16, Los Angeles, CA, Dec. 18-20, 2000.

Mitra, S., and E. J. McCluskey, ``Design Diversity for Concurrent Error Detection in Sequential Logic Circuits," VTS'01, pp. 178-183.

Mitra, S., and E. J. McCluskey, ``Design of Redundant Systems Protected Against Common-Mode Failures," VTS'01, pp. 190-195.

Mitra, S., N. R. Saxena, and E. J. McCluskey, ``Techniques for Estimation of Design Diversity for Combinational Logic Circuits," DSN'01, pp. 25-34.

Mitra, S., Nirmal Saxena and Edward J. McCluskey, ``Evaluation and Design of Dependable Systems with Design Diversity," Evaluating and Architecting System Dependability, July 2001.

Mitra, S., Chao-wen Tseng, James Li and Edward J. McCluskey, ``Pseudo-Random Testing: Theoretical Models vs. Real Data," IEEE Int. Test Resource Partitioning Workshop, Baltimore, Nov. 2001.

Mitra, S., Edward J. McCluskey and Samy Makar, ``Design for Testability and Testing of IEEE 1149.1 TAP Controller," VTS'02, pp. 247-252.

Mitra, S. Nirmal Saxena and Edward J. McCluskey, ``A Design Diversity Metric and Analysis of Redundant Systems," IEEE Transactions on Computers, Vol. 51, No. 5, pp. 498-510, May 2002.

Mitra, S. and Edward J. McCluskey, ``Dependable Reconfigurable Systems: Design Diversity and Self-Repair," Invited Talk, Int. Conference on Evolvable Hardware, July 2002.

Mitra, S., W. Huang. N.R. Saxena, S. Yu and E.J. McCluskey, ``Reconfigurable Architecture for Autonomous Self-Repair," IEEE Design & Test of Computers, Special Issue on Yield & Reliability, Vol. 21, Issue 3, pp. 228-240, May-June 2004.

Mitra, S., Nirmal Saxena, and E.J. McCluskey, ``Efficient Design Diversity Estimation for Combinational Circuits," IEEE Trans. Comp., Vol. 53, Issue 11, pp. 1,483-1,492, Nov. 2004.

Mitra, S., E. Volkerink, E.J. McCluskey and S. Eichenberger, ``Delay Defect Screening using Process Monitor Structures," VTS'04, pp. 43-48, 2004.

Mourad, S., and D. Andrews, ``On the Reliability of the IBM/MVS/XA," CRC TR 85-1.

Mourad, S., and D. M. Andrews, ``The Reliability of the IBM MVS/XA Operating System," FTC'85, pp. 93-98. (CRC TR 85-3)

Mourad, S., J. L. A. Hughes, and E. J. McCluskey, "Multiple Fault Detection in Parity Trees," COMPCON'86, pp. 441-444.

Mourad, S., J. A. Hughes, and E. J. McCluskey, "Stuck-At Fault Detection in Parity Trees," Proc., Ninth Fault-Tolerant Systems and Diagnostics (FTSD'86), pp. 142-147, Brno, Czechoslovakia, June 1986, and FJCC'86, Dallas, TX, pp. 836-840, Nov. 1986. (CRC TR 85-23 and 86-7)

Mourad, S., ``Design or Test, Logic Design and Digital Testing in CS and EE Curricula," Test Technology Workshop, Washington, D.C., Sep. 11, 1986. (CRC TR 86-12)

Mourad, S., J. L. A. Hughes, and E. J. McCluskey, ``Effectiveness of Single Stuck-at Fault Tests in Detecting Multiple Faults," Int. Journ. of Comput. and Math. Appl., Vol. 13, pp. 455-459, May/June 1987.

Mourad, S., and E. J. McCluskey, ``On Benchmarking Digital Testing Systems," ITC'88, Poster Session, pp. 997. (CRC TR 88-5)

Mourad, S., ``Digital Testing: Theory and Practice," ITC'88, pp. 205-206. (CRC TR 88-5)

Mourad, S., and E. J. McCluskey, ``Fault Models," in Testing and Diagnosis of VLSI and ULSI, pp. 49-68, Kluwer Academic Publishers, 1988.

Mourad, S., and E. J. McCluskey, ``Testability of Parity Checkers," IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, pp. 254-262, May 1989.

Mourad, S., and E. J. McCluskey, ``Fault Analysis Using Signature Analyzers," 1989 Int. Conference on Circuits and Systems, Nanjing, China, July 6-9, 1989. (CRC TR 89-3)

Mourad, S., M. Martonosi, and E. J. McCluskey, "Benchmarking Magnitude Comparators," Fourth Technical Workshop: New Directions for IC Testing, Victoria, B.C., Canada, Oct. 24-26, 1989.

Mukund, S. K., E. J. McCluskey, and T. R. N. Rao, ``An Apparatus for Pseudo-Deterministic Testing," CRC TR 94-12.

Mukund, S. K., E. J. McCluskey, and T. R. N. Rao, ``An Apparatus for Pseudo-Deterministic Testing," VTS'95, pp. 125-131.

Munda, S. V., ``Bibliography of 1988 CRC Publications," CRC TR 89-0.

Munda, S. V., ``Bibliography of 1989 CRC Publications," CRC TR 90-0.

Munda, S.V., ``Bibliography of the 1990 CRC Publications," CRC TR 91-0.

Munda, S.V., ``Bibliography of the 1991 CRC Activities," CRC TR 92-0.

Munda, S.V., ``Biobliography of the 1992 CRC Activities," CRC TR 93-0.

Munda, S.V., ``Bibliography of 1969-1992 CRC Publications," CRC TR 93-3.

Munda, S.V., ``Bibliography 1993 CRC Activities," CRC TR 94-0.

Munda, S.V., ``Bibliography 1994 CRC Activities," CRC TR 95-0.

Munda, S.V., ``Bibliography 1995 CRC Activities," CRC TR 96-0.

Munda, S.V., ``Bibliography 1996 CRC Activities," CRC TR 97-0.

Namjoo, M., and E. J. McCluskey, ``Watchdog Processors and Detection of Malfunctions at the System Level," CRC TR 81-17.

Namjoo, M., and E. J. McCluskey, ``Watchdog Processors and Capability Checking," CRC TR 82-3.

Namjoo, M., ``Concurrent Testing Using Path Signature Analysis," CRC TR 82-16.

Namjoo, M., ``Design of Concurrently Testable Microprogrammed Control Units," Proc., Micro-15 Workshop, Palo Alto, CA, pp. 173-180, Oct. 4-7, 1982. (CRC TR 82-6 and 82-14)

Namjoo, M., ``Techniques for Concurrent Testing of VLSI Processor Operation," ITC'82, pp. 461-468. (CRC TR 82-13)

Namjoo, M., ``Cerberus-16: An Architecture for a General Purpose Watchdog Processor," FTC'83, pp. 216-219. (CRC TR 82-19 and 83-3)

Nanya, T., and H. A. Goosen, ``Effect of Byzantine Hardware Faults on Concurrent Error Checking," ICCAD'87, pp. 242-245. (CRC TR 87-18)

Nanya, T., S. Mourad, and E. J. McCluskey, "Multiple Stuck-at Fault Testability of Self-testing Checkers,"FTC'88, pp. 381-386. (CRC TR 88-5)

Nassar, F. A., and D. M. Andrews, ``A Methodology for Analysis of Failure Prediction Data," Real-Time Systems Symposium, San Diego, CA, pp. 160-166, Dec. 3-5, 1985. (CRC TR 85-4 and 85-20).

Norman, R. H., and E. J. McCluskey, ``Design for Integrity," Advanced Microelectronics Technology Qualification, Reliability and Logistics Workshop, San Diego, CA, Aug. 28-30, 1990.

Norwood, R. B., and E. J. McCluskey,`` Synthesis-for-Scan and Scan Chain Ordering," VTS'96, pp. 87-92, Princeton, NJ, Apr. 28-May 1, 1996.

Norwood, R. B., and E. J. McCluskey, `` Orthogonal Scan Paths for Data Path Logic," Third Int. Test Synthesis Workshop, Santa Barbara, CA, May 6-8, 1996.

Norwood, R. B., and E. J. McCluskey, ``Orthogonal Scan: Low-Overhead Scan for Data Paths," ITC'96, pp. 659-668.

Norwood, R. B., and E. J. McCluskey, `` High-Level Synthesis for Scan," VTS'97, pp. 370-375. (CRC TN 96-4)

Norwood, R. B., and E. J. McCluskey, ``Delay Testing of Data Paths with Scan," Fourth IEEE Intl. Test Synthesis Workshop, Santa Barbara, CA, May 5-7, 1997

Norwood, R. B., and E. J. McCluskey, ``Synthesis-for-Scan and Scan Path Ordering," CRC TR 97-3.

Norwood, R. B., and E. J. McCluskey, ``Merged Orthogonal Scan," CRC TR 97-4.

Norwood, R. B., and E. J. McCluskey, ``Delay Testing for Sequential Circuits with Scan," CRC TR 97-5.

Ogus, R. C., ``The Probability of a Correct Output >From a Combinatorial Circuit," FTC'74, and IEEE Trans. Comput, Vol. C-24, No. 5, pp. 534-544, May 1975. (CSL TN 35)

Ogus, R. C., ``Reliability Analysis of Hybrid Redundant Systems with Nonperfect Switches," CSL TR 65.

Ogus, R. C., ``Fault-tolerance of the Iterative Cell Array Switch for Hybrid Redundancy," IEEE Trans. Comput., C-23, No. 7, July 1974, pp. 667-682. (CSL TR 55)

Oh, N., P. P. Shirvani, and E. J. McCluskey, ``Control Flow Checking by Software Signatures," CRC TR 00-04, Apr. 2000.

Oh, N., P. P. Shirvani, and E. J. McCluskey, ``Error Detection by Duplicating Instructions in Super-scalar Processors," CRC TR 00-5, Apr. 2000.

Oh, N., S. Mitra, and E. J. McCluskey, ``ED4I: Error Detection by Diverse Data and Duplicated Instructions," CRC TR 00-8, Apr. 2000.

Oh, N., S. Mitra and E.J. McCluskey, ``ED4I: Error Detection by Diverse Data and Duplicated Instructions," IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems, Vol. 51, Issue 2, pp. 180-199, Feb. 2002.

Owicki, S. S., ``Specifications and Proofs for Abstract Data Types in Concurrent Programs," CSL TR 133.

Owicki, S. S., ``Verifying Concurrent Programs with Shared Data Classes," CSL TR 147.

Pan, R., N. A. Touba, and E. J. McCluskey, ``The Effect of Fault Dropping on Fault Simulation Time," CRC TR 93-5.

Park, I., D. Lee, E. Chmelar, and E. J. McCluskey, ``Inconsistent Fails Due to Limited Tester Timing Accuracy," VTS'08, pp. 47-52.

Park, I., A. Al-Yamani, and E. J. McCluskey, ``Effective TARO Pattern Generation," VTS'05.

Park, I., E. Chmelar, and E. J. McCluskey, ``ELF18 Test Environment and Defect Classification," CRC TR 07-01, 2007.

Parker, K. P., ``Probabilistic Test Generation," CSL TN 18.

Parker, K. P., and E. J. McCluskey "Probabilistic Treatment of General Combinational Networks," IEEE Trans. Comput., Vol. C-24, No. 6, pp. 668-670, June 1975. (CSL TN 20)

Parker, K. P., and E. J. McCluskey, ``Analysis of Logic Circuits with Faults Using Input Signal Probabilities," IEEE Trans. Comput., Vol. C-24, No. 5, May 1975. (CSL TN 21)

Parker, K. P., ``Adaptive Random Test Generation," Journ. Design Automation and Fault-Tolerant Computing, Vol. 1, No. 1, pp. 62-83, Oct. 1976. (CSL TN 73 and 109)

Parker, K. P., ``Compact Testing: Testing with Compressed Data," FTC'76, pp. 93-98. (CSL TN 64)

Parker, K. P., and E. J. McCluskey, ``Sequential Circuit Output Probabilities from Regular Expressions," IEEE Trans. Comput., pp. 222-231, Mar. 1978. (CSL TR 93)

Patashnik, O., ``Circuit Segmentation for Pseudo-exhaustive Testing," CRC TR 83-14.

Peterson, J. L., and T. H. Bredt, ``A Comparison of Models for Parallel Systems," Proc., 1974 IFIP Congress, Stockholm, Sweden, Aug. 5-10, 1974.

Pradhan, D. K., ``Design of Easily Testable Sequential Machines Using Extra Inputs," CSL TN 173.

Reddy, B. M., ``Synthesis Tool for Ethernet PAM (Pulse Amplitude Modulator) Encoder," CRC TR 04-04
, October 2004.

Reese, R. D., and E. J. McCluskey, ``A Gate Equivalent Model for Combinational Logic Network Analysis," Dig., Third Ann. Symp. on Fault-Tolerant Computing, Palo Alto, CA, June 20-22, 1973, pp. 79-85. (CSL TN 28)

Robinson, J. P., and N. R. Saxena, ``Simultaneous Signature and Syndrome Compression," IEEE Trans. CAD, Vol. 7, No. 5, pp. 584-589, May 1988.

Rossetti, D. J., and T.H. Bredt, ``The Design and Implementation of an Operating System Tracer," CSL TN 97.

Rossetti, D. J., and R. K. Iyer, ``A Software System for Reliability and Workload Analysis," CRC TR 81-18.

Rossetti, D. J., and R. K. Iyer, ``Analysis of Software Related Failures on the IBM 3081: Relationship with System Utilization," CRC TR 82-8.

Rossetti, D. J., and R. K. Iyer, ``Software Related Failures on the IBM 3081: A Relationship with System Utilization," COMPSAC'82, pp. 45-54.

Sakov, J., and E. J. McCluskey, ``Functional Test Pattern Generation for Random Logic," CRC TR 87-1.

Savir, J., ``Optimal Random Testing of Single Intermittent Failures in Combinational Circuits," FTC'77, pp. 180-185. (CSL TN 105)

Savir, J., ``Detection of Single Faults in Modular Combinational Networks," CSL TN 136.

Savir, J., ``Detection of Intermittent Faults in Sequential Circuits," CSL TR 120.

Savir, J., ``Testing For Multiple Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection," FTC'78, p. 212. (CSL TR 146)

Savir, J., ``Testing for Intermittent Failures in Combinational Circuits by Minimizing the Mean Testing Time for a Given Test Quality," USA-Japan'78, pp. 155-161. (CSL TR 148)

Savir, J., ``Model and Random-Testing Properties of Intermittent Faults in Combinational Circuits," Design Automation & Fault-Tolerant Computing, pp. 215-230, 1978. (CSL TN 118)

Savir, J., ``Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection," IEEE Trans. Comput., Vol. C-29, No. 5, pp. 410-416, May 1980. (CSL TR 145)

Savir, J., ``Syndrome-Testable Design of Combinational Circuits," IEEE Trans. Comput., Vol. C-29, No. 6, pp. 442-451, June 1980. (CSL TR 157)

Saxena, N. R., and E. J. McCluskey, ``Extended Precision Checksums," FTC'87, pp. 142-147.

Saxena, N. R., and J. P. Robinson, ``Syndrome and Transition Count are Uncorrelated," IEEE Trans. on Info. Theory, Vol. 34, No. 1, pp. 64-69, Jan. 1988.

Saxena, N. R., and E. J. McCluskey, ``Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums," FTC'89, pp. 428-435, and IEEE Trans. Comput., Vol. 39, No. 4, pp. 554-559, Apr. 1990. (CRC TR 89-2)

Saxena, N. R., and E. J. McCluskey, ``Arithmetic and Galois Checksums," ICCAD'89, pp. 570-573. (CRC TR 89-3)

Saxena, N. R., and E. J. McCluskey, ``Analysis of Checksums, Extended-Precision Checksums and Cyclic Redundancy Checks," IEEE Trans. Comput., Vol. 39, No. 7, pp. 969-975, July 1990. ( CRC TR 88-9)

Saxena, N. R., and E. J. McCluskey, ``Bounds on Aliasing Probabilities under Bernoulli Error Model for Signature Analysis," ITC'90, Poster Session.

Saxena, N. R., E. J. McCluskey, and P. Franco, ``Bounds on Signature Analysis Aliasing for Random Testing," CRC TR 90-11.

Saxena, N. R., E. J. McCluskey, and P. Franco, ``Refined Bounds on Signature Analysis Aliasing for Random Testing," CRC TR 91-2.

Saxena, N. R., E. J. McCluskey, and S. Makar, s``"Linear Complexity Assertions for Sorting Algorithms," CRC TR 91-3.

Saxena, N. R., and E. J. McCluskey, ``Bounds on Signature Analysis Aliasing for Random Testing," FTC'91, pp. 104-111. (CRC TR 91-4)

Saxena, N. R., E. J. McCluskey, and P. Franco, ``Refined Bounds on Signature Analysis Aliasing for Random Testing," ITC'91, pp. 818-827. (CRC TR 91-5)

Saxena, N. R., P. Franco, and E. J. McCluskey, ``Simple Bounds on Signature Analysis Aliasing for Random Testing," Special Issue on Fault-Tolerant Computing, IEEE Trans. Comput, pp. 638-645, May 1992.

Saxena, N. R., and E. J. McCluskey, ``Linear Complexity Assertions for Sorting Algorithms," IEEE Trans. Software Eng., Vol. 20, No. 6, pp. 424-431, June 1994.

Saxena, N. R., and E. J. McCluskey, ``Counting Two-State Transition-Tour Sequences," IEEE Trans. Comput., Vol. 45, No. 11, pp. 1337-1342, Nov. 1996.

Saxena, N. R., and E. J. McCluskey, ``Parallel Signature Analysis Design with Bounds on Aliasing," IEEE Trans. Comput., Vol. 46, No. 4, pp. 425-438, Apr. 1997

Saxena, N. R., and E. J. McCluskey, `` Dependable Adaptive Computing Systems," IEEE Systems, Man, and Cybernetics Conf., San Diego, CA, pp. 2172-2177, Oct. 11-14, 1998.

Saxena, N. R., and E. J. McCluskey, ``Fault-Tolerance with Multithreaded Computing - A New Approach," FTC'99, Fast Abstracts, pp. 29-30.

Saxena, N. R., S. Fernandez-Gomez, W. J. Huang, S. Mitra, S.-Y. Yu and E. J. McCluskey, ``Dependable Computing and Online Testing in Adaptive and Configurable Systems," IEEE Design and Test of Computers, Vol. 17, No. 1, pp. 29-41, Jan.-Mar. 2000.

Saxena, N. R., and E. J. McCluskey, ``Primitive Polynomial Generation Algorithms Implementation and Performance Analysis," CRC TR 04-03, April 2004.

Shedletsky, J. J., ``A Rationale for the Random Testing of Combinational Digital Circuits," COMPCON'75, pp. 5-8.

Shedletsky, J. J., and E. J. McCluskey, ``The Error Latency of a Fault in a Combinational Digital Circuit," CSL TN 55.

Shedletsky, J. J., and E. J. McCluskey, ``The Error Latency of a Fault in a Sequential Digital Circuit," FTC'75, pp. 210-214, and IEEE Trans. Comput., C-25, No. 6, pp. 655-659, June 1976. (CSL TN 56)

Shedletsky, J. J., ``A Rollback Interval for Networks with an Imperfect Self-checking Property," FTC'76, pp. 163-168. (CSL TR 96)

Shedletsky, J. J., ``Error Latency of a Combinational Digital Circuit," CSL TR 103.

Shedletsky, J. J., ``Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder," IEEE Trans. Comp., pp. 271-272, Mar. 1977. (CSL TN 78)

Shedletsky, J. J., ``Random Testing: Practicality vs. Verified Effectiveness," FTC'77, pp. 175-179.

Shedletsky, J. J., ``Error Correction by Alternate-Data Retry," IEEE Trans. Comput., pp. 106-112, Feb. 1978. (CSL TN 113)

Shirvani, P. P., and E. J. McCluskey, ``Fault-Tolerant Systems in a Space Environment: The CRC ARGOS Project," CRC-TR 98-2.

Shirvani, P. P., and E. J. McCluskey, ``PADded Cache: A New Fault-Tolerance Technique for Cache Memories," VTS'99 pp. 440-445.

Shirvani, P. P., N. R. Saxena, N. Oh, S. Mitra, S.-Y. Yu, W.-J. Huang, S. Fernandez-Gomez, N. A. Touba and E. J. McCluskey,``Fault-Tolerance Projects at Stanford CRC," Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), Laurel, MD, Sep. 28-30, 1999.

Shirvani,P. P., and E. J. McCluskey, ``PADded Cache: A New Fault Tolerance Technique for Cache Memories," CRC TR 00-6, Apr. 2000.

Shirvani, P. P., N. R. Saxena, and E. J. McCluskey, ``Software-Implemented EDAC Protection Against SEUs," IEEE Trans. on Reliability, Vol. 49, No. 3, pp. 273-284, Sep. 2000. (CRC TR 01-3.)

Shirvani, P. P., and E. J. McCluskey, ``SEU Characterization of Digital Circuits Using Weighted Test Programs," CRC TR 01-4, May 2001.

Shperling, I., and E. J. McCluskey, ``Circuit Segmentation for Pseudo-Exhaustive Testing via Simulated Annealing," ITC'87, pp. 58-65. (CRC TR 87-2 and 87-12)

Siewiorek, D. P., ``On Rapid Calculating Techniques for the Reliability of Serial Triple-Modular Redundancy," CSL TN 5.

Siewiorek, D. P., ``A Re-Evaluation of the Classical Model for NMR Reliability," CSL TN 8.

Siewiorek, D. P., and E. J. McCluskey, ``Switch Designs for Hybrid Redundancy," CSL TN 13.

Siewiorek, D. P., ``A Unifying Perspective of Fault Tolerant Computer Techniques," CSL TN 14.

Siewiorek, D. P., and E. J. McCluskey, ``An Iterative Cell Switch Design for Hybrid Redundancy," CSL TR 20.

Siewiorek, D. P., and E. J. McCluskey, ``A Measure of Switch Complexity in Systems with Standby Spares," CSL TR 21.

Siewiorek, D. P., ``Models of Self-Diagnosable Systems," CSL TR 22.

Siewiorek, D. P., ``An Improved Algorithm for Selecting a Set of Diagnostic Tests," CSL TR 23. >br>
>iewiorek, D. P., ``An Improved Reliability Model for NMR," CSL TR 24.

Siewiorek, D. P., and E. J. McCluskey, ``An Iterative Cell Switch Design for Hybrid Redundancy," IEEE Trans. Comput., C-22, No. 3, Mar. 1973, pp. 290-297.

Siewiorek, D. P., and E. J. McCluskey, ``Switch Complexity in Systems with Hybrid Redundancy," IEEE Trans. Comput., C-22, No. 3, Mar. 1973, pp. 276-282.

Siewiorek, D. P., ``Reliability Modeling of Compensating Failures in Majority Voted Redundancy," FTC'74, pp. 14-19, 1974.

Sun, Z., and L.-T. Wang, ``Self-Testing of Embedded RAMs" ITC'84, pp. 148-156. (CRC TR 84-8)

Svobodova, L., ``Computer System Performance Measurement: Instruction Set Processor Level and Microcode Level," CSL TR 66.

Svobodova, L., ``Computer Performance Measurement and Evaluation Methods; Analysis and Applications," CSL TR 72.

Svobodova, L., ``Monitoring and Controlling Performance of a Large Computer System, COMPCON'74, pp. 79-82.

Sziray, J., ``A Test Calculation Algorithm for Module-level Combinational Networks," Digital Processes, Vol. 5, No. 1-2, pp. 17-26, Spring-Summer 1979. (CSL TN 124)

Sziray, J., ``Test Calculation for Logic Network by Composite Justification," Digital Processes, Vol. 5, No. 1-2, pp. 3-16, Spring-Summer 1979. (CSL TN 129)

Thompson, P. A., ``A Simulator for the Evaluation of Reliability," CSL TN 106.

Thompson, P. A., ``Critique of the SIRU Dual Computer System," CSL TN 111.

Thompson, P. A., ``A Simulator for the Evaluation of Digital System Reliability," CSL TR 119.

Thompson, P. A., ``Using Simulation to Evaluate the Reliability of a Dual Computer System," CSL TR 121.

Thompson, P. A., ``Manual for a General-Purpose Simulator Used to Evaluate Reliability of Digital Systems," CSL TR 132.

Touba, N., ``Reducing Synchronization in Concurrent Behavioral Descriptions," CRC TR 92-3.

Touba, N. A., and E. J. McCluskey, ``Logic Synthesis for Concurrent Error Detection," CRC TR 93-6.

Touba, N. A., and E. J. McCluskey, ``Logic Synthesis of Random Pattern Testable Circuits Using Algebraic Transformations," First Int. Test Synthesis Workshop, Poster Session, Santa Barbara, CA, May 18-20, 1994.

Touba, N. A., and E. J. McCluskey, ``Automated Logic Synthesis of Random Pattern Testable Circuits," ITC'94, pp. 174-183. (CRC TR 94-6)

Touba, N. A., and E. J. McCluskey, ``Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection," ICCAD'94, pp. 651-654. (CRC TR 94-6)

Touba, N. A., and E. J. McCluskey, ``Transformed Pseudo-Random Patterns for BIST," CRC TR 94-10.

Touba, N. A., and E. J. McCluskey, ``Transformed Pseudo-Random Patterns for BIST," VTS'95, pp. 410-416.

Touba, N. A., and E. J. McCluskey, ``Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST," ITC'95, pp. 674-682.

Touba, N. A., and E. J. McCluskey,``Applying Two-Pattern Tests Using Scan-Mapping," VTS'96, pp. 393-397.

Touba, N. A., and E. J. McCluskey,``Test Point Insertion Based on Path Tracing," VTS'96, pp. 2-8.

Touba, N. A., and E. J. McCluskey, ``Altering a Pseudo-Random Bit Sequence for Mixed-Mode Scan BIST," Third Int. Test Synthesis Workshop, Santa Barbara, CA, May 6-8, 1996.

Touba, N. A., and E. J. McCluskey, ``Test Point Insertion for Non-Feedback Bridging Faults," CRC TR 96-3.

Touba, N. A., and E. J. McCluskey, ``Altering a Pseudo-Random Bit Sequence for Scan-Based BIST," ITC'96, pp. 167-175.

Touba, N. A., and E. J. McCluskey, ``Partial Isolation Rings for Testing Embedded Cores," IEEE Int. High Level Design Validation and Test Workshop, Oakland, CA, Nov. 15-16, 1996.

Touba, N. A., and E. J. McCluskey, ``Logic Synthesis of Multilevel Circuits with Concurrent Error Detection," IEEE Trans. CAD, Vol. 16, No. 7, pp. 783-789, July 1997.

Touba, N. A., and E. J. McCluskey, ``Pseudo-Random Pattern Testing of Bridging Faults," ICCD'97. (CRC TR 97-2)

Touba, N. A., and E. J. McCluskey, ``RP-SYN: Synthesis of Random Pattern Testable Circuits with Test Point Insertion," IEEE Trans. CAD., Vol. 18, No. 8, pp. 1202-1213, Aug. 1999.

Touba, N. A., and E. J. McCluskey, ``Bit-Fixing in Pseudorandom Sequences for Scan BIST," IEEE Trans. CAD., Vol. 20, No. 4, pp. 545-555, Apr. 2001.

Tseng, C.-W., E. J. McCluskey, X. Shao, J. Wu, and D. M. Wu., ``Cold Delay Defect Screening," VTS'00 pp. 183-188.

Tseng, C.-W., R. Chen, P. Nigh, and E. J. McCluskey, ``MINVDD Testing for Weak CMOS ICs," VTS'01, pp. 339-344.

Tseng, C.-W., S. Mitra, S. Davidson, and E. J. McCluskey, ``An Evaluation of Pseudo Random Testing for Detecting Real Defects," VTS'01, pp. 404-409.

Turcat, C., and A. Verdillon, ``Recursion and Testing of Combinational Circuits," IEEE Trans. Comput., Vol. C-25, No. 6, pp. 652-654, June 1976.

Udell, J. G. Jr., ``Test Set Generation for Pseudo-Exhaustive BIST," ICCAD'86, pp. 52-55. (CRC TR 86-14 and 87-3)

Udell, J. G. Jr., and E. J. McCluskey, ``Efficient Circuit Segmentation for Pseudo-Exhaustive Test," ICCAD'87, pp. 148-151. (CRC TR 87-18)

Udell, J. G. Jr., ``Reconfigurable Hardware for Pseudo-Exhaustive Test," ITC'88, pp. 522-530. (CRC TR 87-4 and 88-5)

Udell, J. G. Jr., and E. J. McCluskey, ``Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation," ITC'88, Poster Session, pp. 1000. (CRC TR 88-5 and 88-7)

Udell, J. G. Jr., and E. J. McCluskey, ``Circuit Reduction for Efficient Segmentation," CRC TR 88-10.

Udell, J. G. Jr., and E. J. McCluskey, ``An Efficient Segmentation Program for Pseudo-Exhaustive Test," CRC TR 88-11.

Udell, J. G. Jr., and E. J. McCluskey, ``Pseudo-Exhaustive Test and Segmentation: Formal Definitions and Extended Fault Coverage Results," CRC TR 88-12.

Udell, J. G. Jr., ``Pseudo-Exhaustive Testing of Digital Integrated Circuits," CRC TR 89-1.

Udell, J. G. Jr., and E. J. McCluskey, ``Pseudoexhaustive Test and Segmentation; Formal Definitions and Extended Fault Coverage Results," FTC'89, pp. 292-298. (CRC TR 89-2)

Usas, A. M., ``The Detection of Errors in Periodic Signals," CSL TN 45.

Usas, A. M., and E. J. McCluskey, ``Design and Application of a Self-checking Periodic-signal Checker," COMPCON'74, pp. 83-91.

Usas, A. M., ``Fail-Safe Circuits: A means to Improve Reliability and Maintainability of I/O Subsystems," COMPCON'75. (CSL TN 59)

Usas, A. M., ``A Totally Self-checking Checker Design for the Detection of Errors in Periodic Signals," IEEE Trans. Comput., Vol. C-24, No. 5, pp. 483-489, May 1975.

Usas, A. M., ``Error Management in Digital Computer Input/output Systems," CSL TR 122.

Velardi, P., and R. K. Iyer, ``A Study of Software Failures and Recovery in the MVS Operating System," IEEE Trans. Comput., Vol. C-33, No. 6, pp. 564-568, June 1984. (CRC TR 83-7)

Verdillon, A., ``Procedures to Obtain Optimal Test Sequences," FTC'76, p. 200. (CSL TN 80)

Verdillon, A., ``Symmetry, Automorphism and Test," CSL TN 87.

Volkerink, E., and S. Mitra, ``Packet-based Input Test Data Compression Techniques," ITC'02, pp. 671-700.

Volkerink, E., and S. Mitra, ``Packet-based Test Response Compression in the Presence of any Number of Unknowns," First IEEE Infra-Structure IP workshop in conjunction with ITC'03, 2003.

Volkerink, E., and S. Mitra, ``Efficient Seed Utilization for Reseeding based Compression," VTS'03.

E. Volkerink and S. Mitra, ``Test Response Compression with Any Number of Unknowns," DAC'05, 2005.

Wagner, K. D., ``Design for Testability in the Amdahl 580," COMPCON'83, pp. 384-388. (CRC TR 82-20)

Wagner, K. D., and E. J. McCluskey, ``Tuning, Clock Distribution and Communication in VLSI High-Speed Chips," CRC TR 84-5.

Wagner, K. D., ``Delay Testing of Digital Circuits Using Pseudorandom Input Sequences," CRC TR 85-12.

Wagner, K. D., ``The Error Latency of Delay Faults in Combinational and Sequential Circuits," ITC'85, pp. 334-341. (CRC TR 85-11)

Wagner, K. D., and E. J. McCluskey, ``Effect of Supply Voltage on Circuit Propagation Delay and Test Applications," ICCAD'85, pp. 42-44, Nov. 18-21, 1985. (CRC TR 85-17)

Wagner, K. D., C. K. Chin, and E. J. McCluskey, "Fault Coverage of Pseudorandom Testing," ICCAD'86, pp. 48-51. (CRC TR 86-14)

Wagner, K. D., C. K. Chin, and E. J. McCluskey, "Pseudorandom Testing," IEEE Trans. Comput., Vol. C-36, No. 3, pp. 332-343, Mar. 1987.

Wakerly, J. F., ``Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes," IEEE Trans. Comput., Vol. C-24, No. 2, pp. 210-212, Feb. 1975. (CSL TN 26)

Wakerly, J. F., ``Transient Failures in Triple Modular Redundancy Systems with Sequential Modules," IEEE Trans. Comput., Vol. C-24, No. 5, pp. 570-573, May 1975. (CSL TN 23)

Wakerly, J. F., ``Low-Cost Error Detection Techniques for Small Computers," CSL TR 51.

Wakerly, J. F., ``Checked Binary Addition Using Parity Prediction and Checksum Codes," CSL TN 39.

Wakerly, J. F., ``Partially Self-checking Circuits and Their Use in Performing Logical Operations," IEEE Trans. Comput., C-23, No. 7, July 1974, pp. 658-667. (CSL TR 50)

Wakerly, J. F., and E. J. McCluskey, ``Design of Low-cost General-purpose Self-diagnosing Computers," Information Processing Congress, Stockholm, Sweden, Aug. 5-10, 1974, Vol. 1, pp. 108-111. (CSL TN 38)

Wakerly, J. F., Comments on "Asynchronous Sequential Machines Designed for Fault Detection," IEEE Trans. Comput., Vol. C-24, No. 7, p. 760, July 1975.

Wakerly, J. F., C. R. Hollander, and D. Davies, ``Placement of Micro-instructions in a Two-Dimentional Address Space," Proc. Eight Annual Workshop on Microprogramming, Chicago, IL, pp. 46-51, Sep. 1975.

Wakerly, J. F., ``Eliminating the Unwanted Zero in Ones' Complement Addition," CSL TN 71.

Wakerly, J. F., ``One's Complement Adder Eliminates Unwanted Zero," Electronics, Vol. 49, No. 3, pp. 103-105, Feb. 5, 1976.

Wakerly, J. F., ``Principles of Self-Checking Processor Design and an Example," CSL TR 115.

Wakerly, J. F., ``Reliability of Microcomputer Systems Using Triple Modular Redundancy," COMPCON'76, pp. 23-26. (CSL TN 61)

Wakerly, J. F., ``Checked Binary Addition with Checksum," Journ. Design Automation & Fault-Tolerant Computing, Vol. 1, No. 1, pp. 18-27, Oct. 1976.

Wakerly, J. F., ``Microcomputer Reliability Improvement Using Triple Modular Redundancy," Proc., IEEE, Vol. 64, No. 6, pp. 889-895, June 1976.

Wakerly, J. F., ``Design of a Self-Checking Microprogrammed Processor," FTC'76, p. 191.

Wakerly, J. F., and E. J. McCluskey, ``Microcomputers in the Computer Engineering Curriculum," Computer, Vol. 10, No. 1, pp. 32-38, Jan. 1977.

Wakerly, J. F., ``Microprocessor Input/output Architecture," Computer, Vol. 10, No. 2, pp. 26-33, Feb. 1977.

Wakerly, J. F., and E. J. McCluskey, ``Logic Design Education at Stanford University," CRC TR 87-19.

Wakerly, J. F., ``A Designers Guide to Synchronizers and Metastability," CRC TR 88-1.

Wang, D. T., ``An Algorithm for the Generation of Test Sets for Combinational Networks," IEEE Trans. Comput., Vol. C-24, No. 7, pp. 742-746, July 1975.

Wang, D. T., ``Properties of Faults and Criticality of Values Under Tests For Combinational Networks," IEEE Trans. Comput., Vol. C-24, No. 7, pp. 746-750, July 1975.

Wang, L-T., ``Autonomous Linear Feedback Shift Register with On-Line Fault-Detection Capability," FTC'82, pp. 311-314. (CRC TR 82-3)

Wang, L.-T., and E. J. McCluskey, ``A New Condensed Linear Feedback Shift Register Design for VLSI/System Testing," FTC'84, pp. 360-365. (CRC TR 84-2)

Wang, L.-T., and E. Law, ``DTA: Daisy Testability Analyzer," ICCAD'84, pp. 143-145. (CRC TR 84-10)

Wang, L.-T., and E. J. McCluskey, ``Built-In Self Test for Random Logic," Proc., 1985 Int. Symposium on Circuits and Systems, Vol. 3, Kyoto, Japan, pp. 1305-1308, June 5-7, 1985. (CRC TR 85-5)

Wang, L.-T., and E. Law, ``An Enhanced Daisy Testability Analyzer (DTA)," Proc., 1985 IEEE AUTOTESTCON Conf., Long Island, New York, pp. 223-229, Oct. 21-24, 1985. (CRC TR 85-13)

Wang, L.-T., and E. J. McCluskey, ``Condensed Linear Feedback Shift Register (LFSR) Testing -- A Pseudo-Exhaustive Test Technique," IEEE Trans. Comput., Vol. C-35, No. 4, pp. 367-370, Apr. 1986. (CRC TR 85-24)

Wang, L.-T., and E. J. McCluskey, ``Concurrent Built-In Logic Block Observer (CBILBO)," ISCAS'86, pp. 1054-1057. (CRC TR 86-1)

Wang, L.-T., and E. J. McCluskey, ``Circuits for Pseudo-Exhaustive Test Pattern Generation," ITC'86, pp. 25-37. (CRC TR 86-5)

Wang, L.-T., and E. J. McCluskey, ``A Hybrid Design of Maximum-Length Sequence Generators," ITC'86, pp. 38-47. (CRC TR 86-5)

Wang, L.-T, and E. J. McCluskey, ``Complete Feedback Shift Register Design for Built-In Self-Test," ICCAD'86, pp. 56-59. (CRC TR 86-14 and 86-17)

Wang, L.-T., and E. J. McCluskey, ``Feedback Shift Registers for Self-Testing Circuits," VLSI Systems Design, pp. 50-58, Dec. 1986.

Wang, L.-T., ``Circuits for Built-In Self-Test," CRC TR 87-14.

Wang, L.-T., N.E. Hoover, E.H. Porter, and J. J. Zasio, ``SSIM: A Software Levelized Compiled-Code Simulator," DAC'87, pp. 2-8.

Wang, L.-T., and E. J. McCluskey and S. Mourad, "Shift Register Testing of Sequential Machines," FTC'87, pp. 66-71.

Wang, L.-T., and E. J. McCluskey, ``Built-In Self-Test for Sequential Machines," ITC'87, pp. 334-41. (CRC TR 87-12)

Wang, L.-T., and E. J. McCluskey, ``Circuits for Pseudo-Exhaustive Test Pattern Generation Using Shortened Cyclic Codes," ICCD'87, pp. 450-453, Oct. 1987.

Wang, L.-T., and E. J. McCluskey, ``Hybrid Designs Generating Maximum Length Sequences," IEEE Trans. CAD, Vol. 7, No. 1, pp. 91-99, Jan. 1988.

Wang, L.-T., and E. J. McCluskey, ``Linear Feedback Shift Register Design Using Cyclic Codes," IEEE Trans. Comput., Vol. 37, No. 10, pp. 1302-1306 Oct. 1988.

Wang, L.-T., and E. J. McCluskey, ``Circuits for Pseudo-Exhaustive Test Pattern Generation Using Cyclic Codes," IEEE Trans. CAD, Vol 7, No. 10, pp. 1068-1080, Oct. 1988.

Wang, L.-T., and S. Mourad, ``Scan Self-Test For Sequential Machines," Systems Design and Networks Conference, Santa Clara, CA, pp. 19-25, Apr. 17-19, 1988.

Wang, L.-T., M. Marhoefer, and E. J. McCluskey, "A Self-Test and Self-Diagnosis Architecture for Boards Using Boundary Scans," European Test Conference, Paris, France, pp. 119-126, Apr. 12-14, 1989. (CRC TR 89-2)

Wang, L.-T., and S. Mourad, ``SST: Scan self-test for sequential machines," IEE Proceedings-E Computers and Digital Techniques, Vol. 136, pt. E, No. 6, pp. 569-574, Nov. 1989.

Yamamura, H., and E. J. McCluskey, ``Fault Analysis of ECL Gates with Device Defects using SPICE," CRC TR 90-1.

Yamamura, H., ``A Scheme to Detect Non-Functional Faults in ECL Circuits," CRC TR 90-6.

Yamauchi, H., ``Mixed Level and High Level ATPG," CRC TR 90-10.

Xu, X., and E. J. McCluskey, ``Test Generation and Fault Diagnosis for Multiple Faults in Combinational Circuits," FTC'83, pp. 110-113. (CRC TR 83-2)

Xu, X., ``A Modularized Test Generation Method Using Matrices," CRC TR 81-15.

Yu, S.-Y., N. R. Saxena, and E. J. McCluskey ``ACS Implementation of a Robotic Control Algorithm with Fault Tolerant Capabilities," FCCM'00 Symposium on Field-Programmable Custom Computing Machines, pp. 175-184, Napa Valley, CA, April 16-19, 2000.

Yu, S.-Y., and E. J. McCluskey `` On-line Testing and Recovery in TMR Systems for Real-Time Application, " ITC'01, pp. 240-249.

Yu, S.-Y., and E. J. McCluskey ``Permanent Fault Repair for FPGAs with Limited Redundant Area," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), pp. 125-133, San Francisco, CA, 2001.

Yu, S.-Y., and E. J. McCluskey ``Permanent Fault Repair for FPGAs through Graceful Degradation," DSN'01, Fast Abstracts, 2001.

Yu, S.-Y., and E. J. McCluskey ``A Roll-forward Recovery in TMR Systems for Real-time Applications" DSN'01, Fast Abstracts, 2001.

Yu, S.-Y., ``Permanent Fault Repair for FPGAs with Limited Redundant Area," CRC TR 01-2, May 2001.

Zeng, C., and E. J. McCluskey, ``Finite State Machine Synthesis with Concurrent Error Detection," ITC'99, pp. 672-679.



List of Abbrieviations

COMPCON'74

COMPCON Fall 1974, Washington, D.C., Sep. 10-12, 1974.

COMPCON'75

COMPCON Fall 1975, Washington, D.C., Sep. 9-11, 1975.

COMPCON'76

COMPCON Fall 1976, San Francisco, CA, Feb. 24-26, 1976.

COMPCON'77

COMPCON Spring 1977, San Francisco, CA, Feb. 28-Mar. 3, 1977.

COMPCON'79

COMPCON Spring 1979, San Francisco, CA, Feb. 26-Mar. 1, 1979.

COMPCON'81

COMPCON Spring 1981, San Francisco, CA, Feb. 24-26, 1981.

COMPCON'82

COMPCON Spring 1982, San Francisco, CA, Feb. 22-25, 1982.

COMPCON'83

COMPCON Spring 1983, San Francisco, CA, Feb. 28-Mar. 3, 1983.

COMPCON'85

Proc., COMPCON Spring 1985, San Francisco, CA, Feb. 26-28, 1985.

COMPCON'86

Proc., COMPCON Spring 1986, San Francisco, CA, Mar. 1986.

COMPCON'90

Proc., COMPCON Spring 1990, San Francisco, CA, Feb. 26-Mar. 2, 1990.

COMPSAC'82

IEEE Computer Society's Sixth Int. Computer Software & Applications Conference, Chicago, IL, Nov. 10-12, 1982.

DAC'82

Nineteenth Design Automation Conference, Las Vegas, NV, June 14-16, 1982.

DAC'87

Twenty-fourth ACM/IEEE Design Automation Conference, Miami Beach, FL, Jun. 28-Jul. 1, 1987.

DAC'03

Fortieth ACM/IEEE Design Automation Conference, Anaheim, CA, June 2-6, 2003.

DASC'84

AIAA/IEEE Digital Avionics Systems Conf., Baltimore, MD, Dec. 3-6, 1984.

DFT'01

Sixteenth IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, Oct. 24-26, 2001.

DFT'02

Seventeenth IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, BC, Canada, Nov. 6-8, 2002.

DSN'01

Int. Symposium on Dependable Systems and Networks, Gotenberg, Sweden, July 1-4, 2001.

ETC'89

Dig., Fourth Annual Symposium on Fault-Tolerant Computing, Champaign-Urbana, IL, June 19-21, 1974.

FTC'74

Dig., Fourth Annual Symposium on Fault-Tolerant Computing, Champaign-Urbana, IL, June 19-21, 1974.

FTC-75

Dig., Fifth Annual Symposium on Fault-Tolerant Computing, Paris, France, June 18-20, 1975.

FTC'76

Dig., Sixth Annual Symposium on Fault-Tolerant Computing, Pittsburgh, PA, June 21-23, 1976.

FTC'77

Dig., Seventh Annual Symposium on Fault-tolerant Computing, Los Angeles, CA, June 28-20, 1977.

FTC'78

Proc., Eighth Annual Symposium on Fault-Tolerant Computing, Toulouse, France, June 21-23, 1978.

FTC'79

Proc., Ninth Annual Symposium on Fault-Tolerant Computing, Madison, WI, June 20-22, 1979.

FTC'80

Proc., 10th Annual Symposium on Fault-Tolerant Computing, Kyoto, Japan, Oct. 1-3, 1980.

FTC'82

Dig., 1982 Int. Symposium on Fault-Tolerant Computing, Santa Monica, CA, June 22-24, 1982.

FTC'83

Dig., 13th Annual Int. Symposium on Fault-Tolerant Computing, Milan, Italy, June 28-30, 1983.

FTC'84

Dig., Fourteenth Int. Conference on Fault-Tolerant Computing, Kissimmee, FL, June 20-22, 1984.

FTC'85

Proc., Fifteenth Int. Symposium on Fault-Tolerant Computing, Ann Arbor, MI, June 17-21, 1985.

FTC'87

Proc., Seventeenth Int. Symposium on Fault-Tolerant Computing, Pittsburg, PA, July 6-8, 1987.

FTC'88

Proc., Eighteenth Int. Symposium on Fault-Tolerant Computing, Tokyo, Japan, June 27-30, 1988.

FTC'89

Proc., Nineteenth Int. Symposium on Fault-Tolerant Computing, Chicago, IL, June 21-23, 1989.

FTC'91

Dig. 21st Annu. Int. Symposium on Fault-Tolerant Computing, Montreal, Canada, June 25-27, 1991.

FTC'92

Dig. 22nd Annu. Int. Symposium on Fault-Tolerant Computing, Boston, MA, July 8-10, 1992.

FTC'93

Dig. 23rd Annu. Int. Symposium on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993.

FTC'95

Dig. 25th Annu. Int. Symposium on Fault-Tolerant Computing, Pasadena, CA, June 27-30, 1995.

FTC'96

Dig. 26th Annu. Int. Symposium on Fault-Tolerant Computing, Sendai, Japan, June 25-27, 1996.

FTC'99

Dig. 29th Annu. Int. Symposium on Fault-Tolerant Computing, Madison, WI, June 15-18, 1999.

HICSS'85

Proc., Eighteenth Annual Hawaii Int. Conf. on System Sciences, Honolulu, Hawaii, Jan. 2-4, 1985.

ICCAD'84

1984 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 12-15, 1984.

ICCAD'85

1985 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 18-21, 1985.

ICCAD'86

1986 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 11-13, 1986.

ICCAD'87

1987 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 9-12, 1987.

ICCAD'89

1989 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 6-9, 1989.

ICCAD'90

1990 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 11-15, 1990.

ICCAD'92

1992 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 8-12, 1992.

ICCAD'94

1994 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 6-10, 1994.

ICCAD'95

1995 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 5-9, 1995.

ICCAD'96

1996 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 10-14, 1996.

ICCAD'97

1997 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 9-13, 1997.

ICCAD'98

1998 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 8-12, 1998.

ICCAD'99

1999 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 7-11, 1999.

ICCAD'04

2004 IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 7-11, 2004.

ICCD'87

Proc., Int. Conf. Computer Design, Port Chester, NY., Oct. 1987.

ICCD'97

Proc., Int. Conf. Computer Design, Austin, TX, Oct. 12-15, 1997.

ISCAS'86

1986 Int. Symp. on Circuits and Systems, San Jose, CA, May 5-7, 1986.

ISCAS'87

1987 Int. Symp. on Circuits and Systems, Philadelphia, PA, May 1987.

ISCAS'91

1991 Int. Symp. on Circuits and Systems, Singapore, June 11-14, 1991.

ITC'82

Int. Test Conf., Philadelphia, PA, Nov. 16-18, 1982.

ITC'83

Int. Test Conf., Philadelphia, PA, Oct. 18-20, 1983.

ITC'84

Int. Test Conf., Philadelphia, PA, Oct. 15-18, 1984.

ITC'85

Proc., Int. Test Conf., Philadelphia, PA, Nov. 19-21, 1985.

ITC'86

Proc., Int. Test Conf., Washington, DC, Sep. 8-11, 1986.

ITC'87

Proc., Int. Test Conf., Washington, DC, Sep. 1-3, 1987.

ITC'90

Proc., Int. Test Conf., Washington, DC, Sep. 10-12, 1990.

ITC'91

Proc., Int. Test Conf., Nashville, TN, Oct. 29-Nov. 1, 1991.

ITC'92

Proc., Int. Test Conf., Baltimore, MD, Sep. 20-24, 1992.

ITC'93

Proc., Int. Test Conf., Baltimore, MD, Oct. 17-21, 1993.

ITC'94

Proc., Int. Test Conf., Washington, DC, Oct. 2-6, 1994.

ITC'95

Proc., Int. Test Conf., Washington, DC, Oct. 23-25, 1995.

ITC'96

Proc., Int. Test Conf., Washington, DC, Oct. 20-24, 1996.

ITC'97

Proc., Int. Test Conf., Washington, DC, Nov. 3-5, 1997.

ITC'98

Proc., Int. Test Conf., Washington, DC, Oct. 18-23, 1998.

ITC'99

Proc., Int. Test Conf., Atlantic City, NJ, Sep. 28-30, 1999.

ITC'00

Proc., Int. Test Conf., Atlantic City, NJ, Oct. 3-5, 2000.

ITC'01

Proc., Int. Test Conf., Baltimore, MD, Oct. 30-Nov. 1, 2001.

ITC'02

Proc., Int. Test Conf., Baltimore, MD, Oct. 7-10. 2002.

ITC'03

Proc., Int. Test Conf., Charlotte, NC, Sep. 28-Oct. 3, 2003.

ITC'05

Proc., Int. Test Conf., Austin, TX, Nov. 8-11, 2005.

TCAD'04

IEEE Transactions on Computer-Aided Design, 2004.

TRP'02

Third IEEE Int. Workshop on Test Resource Partitioning, Baltimore, MD, Oct. 10-11, 2002.

USA-Japan'78

Proc., 3rd USA-Japan'78 Computer Conf., San Francisco, CA, Oct. 10-12, 1978.

VTS'94

Twelfth IEEE VLSI Test Symp., Cherry Hill, NJ, Apr. 25-28, 1994.

VTS'95

Thirteenth IEEE VLSI Test Symp., Princeton, NJ, Apr. 30-May 3, 1995.

VTS'96

Fourteenth IEEE VLSI Test Symp., Princeton, NJ, Apr. 28-May 1, 1996.

VTS'97

Fifteenth IEEE VLSI Test Symp., Monterey, CA, Apr. 27-30, 1997.

VTS'98

Sixteenth IEEE VLSI Test Symp., Monterey, CA, Apr. 26-30, 1998.

VTS'99

Seventeenth IEEE VLSI Test Symp., Dana Point, CA, Apr. 24-29, 1999.

VTS'00

Eighteenth IEEE VLSI Test Symp., Montreal, Canada, Apr. 30-May 4, 2000.

VTS'01

Nineteenth IEEE VLSI Test Symposium, Los Angeles, CA, Apr. 29-May 3, 2001.

VTS'02

Twentieth IEEE VLSI Test Symposium, Monterey, CA, Apr. 28-May 2, 2002.

VTS'03

Twenty-first IEEE VLSI Test Symposium, Napa Valley, CA, Apr. 27-May 1, 2003.

VTS'04

Twenty-second IEEE VLSI Test Symposium, Napa Valley, CA, Apr. 25-28, 2004.

VTS'05

Twenty-third IEEE VLSI Test Symposium, Palm Springs, CA, May. 1-5, 2005.

VTS'06

Twenty-fourth IEEE VLSI Test Symposium, Berkeley, CA, Apr. 30-May 4, 2006.

VTS'07

Twenty-fifth IEEE VLSI Test Symposium, Berkeley, CA, May 6-10, 2007.

VTS'08

Twenty-sixth IEEE VLSI Test Symposium, San Diego, CA, Apr 27-May 1, 2008.



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