Ahmad Al-Yamani Home Page

Ahmad Al-Yamani, Ph.D.
Assistant Director, Center for Reliable Computing
Consulting Assistant Professor, Department of Electrical Engineering
Stanford University

Education:
Stanford University
Ph.D. in Electrical Engineering, June 2004: Concentration on VLSI design and test, design for testability, and built-in self-test.
M.Sc. in Management Science and Engineering, April 2004: Concentration on Network Systems/Operations Research.
King Fahd University of Petroleum and Minerals
M.Sc. in Computer Engineering, June 1999: Concentration on VLSI physical design automation and iterative heuristics.
B.Sc. in Computer Engineering, June 1997.

Experience:
Consulting Assistant Professor, Electrical Engineering, Stanford University, June 2004 - Present
Assistant Director, Center for Reliable Computing, Stanford University, December 2001 - Present

Teaching a graduate/undergraduate course on Logic Design at Stanford University.
Leading the VLSI test experiments at Stanford University.
Lead the design team of the ELF13 test chip (0.13 micron, 4M gates).
Worked on (currently leading) testing and analyzing the test results of the ELF35 test chip (0.35 micron, 0.5M gates).

Adjunct Faculty, Electrical Engineering, Santa Clara University, Spring 2004

Taught a graduate course on logic synthesis.

Lecturer, Computer Engineering, King Fahd University of Petroleum and Minerals, Summer 1999
Graduate Assistant, Computer Engineering, King Fahd University of Petroleum and Minerals, 1997-1999

Taught introduction to computer engineering (lecture and lab).
Taught personal computers (lab) and digital system design (lab).

Computer Networks Performance Consultant, Advanced Design Lab, Network Products Division, AMD, Summer 2000

Worked on simulating and evaluating some aspects of Home Phoneline Networks.

Systems Analyst, Management Systems, MIC-Proctor&Gamble, Summer 1996

Developed database systems.

Honors and Activities:

First recipient of Gerald Gordon award from the test technology technical council, international test conference, 2003.
First honor student for seven successive years in KFUPM.
Winner of "Best graduate assistant award" in computer engineering at KFUPM 1997.
Member of the organizing committee for 12th and 13th Pacific Northwest Test Workshop (BAST'03 and BAST'04).

Refereed papers for the following conferences and journals:

The Arabian Journal for Science and Engineering.
IEEE International Test Conference.
IEEE VLSI Test Symposium.
IEEE Transactions on Computers.
IEEE Transactions on Computer Aided Design.
IEEE Design Automation Conference.

Publications:

S. Sait, Youssef, Barada, and A. Al-Yamani, "A Parallel Tabu Search Algorithm for VLSI Standard Cell Placement," (ISCAS'00), Geneva, Switzerland, May, 2000.
Al-Yamani, A.A., N. Oh, and E.J. McCluskey, "Algorithm-Based Fault Tolerance: A Performance Perspective Based on Error Rate," Fast Abstract, International Symposium on Dependable Systmes and Networks (DSN'01),Gotenberg, Sweden, July 1-4, 2001.
Al-Yamani, A.A., N. Oh, and E.J. McCluskey,"Performance Evaluation of Checksum-Based ABFT," 16th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), San Francisco, CA, Oct. 24-26, 2001.
Al-Yamani, A.A., and E.J. McCluskey, "Low-Overhead Built-In BIST Reseeding," 3rd IEEE International Workshop on Test Resource Partitioning (TRP'02), Baltimore, MD, Oct. 10-11, 2002.
Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Techniques for Testing Digital Circuits with Constraints," 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), Vancouver,BC, Canada, Nov. 6-8, 2002.
Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Avoiding Illegal States in Pseudorandom Testing of Digital Circuits," CRC TR 02-02
Al-Yamani, A.A., S. Sait and H. Barada, "HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement," Congress on Evolutionary Computing (CEC'02), Honolulu, Hawaii, May 12-17, 2002.
Al-Yamani, A.A., S. Sait and H. Youssef, "Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations," Journal of Heuristics on Parallel Metaheuristics, 8(3), pp. 277-304, May 2002.
Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Built-In Self Test," CRC TR 02-03
Al-Yamani, A.A., S. Sait, H. Youssef, and H. Barada, "Parallel Tabu Search in a Heterogeneous Environment," IEEE International Parallel and Distributed Processing Symposium (IPDPS'03), Nice, France, Apr. 22-26, 2003.
Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Serial BIST," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003.
Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "BIST Reseeding with Very Few Seeds," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003.
Al-Yamani, A.A., and E.J. McCluskey, "Seed Encoding for LFSRs and Cellular Automata," 40th ACM/IEEE Design Automation Conference (DAC'03), Anaheim, CA, June 2-6, 2003.
McCluskey, E.J., A. A. Al-Yamani, C.-M. Li, C.W. Tseng, E. Volkerink, F. Ferhani, E. Li, and S. Mitra,"ELF-Murphy Data on Defects and Test Sets," Proc. 2004 VLSI Test Symposium, Napa Valley, CA, Apr. 25-28, 2004.
Al-Yamani, A.A., and E.J. McCluskey, "Test Quality for High Level Structural Test," High Level Design Validation and Test (HLDVT'04), Sonoma, CA, November 2004.
Salama, K.N., and A.A. Al-Yamani, "Analysis of Self-Correcting Active Pixel Sensors," SPIE's 17th Annual Symposium on Electronic Imaging Science and Technology, San Jose, CA, January 2005.
Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Optimized Reseeding by Seed Ordering and Encoding," IEEE Transactions on Computer-Aided Design (TCAD'05),2005.
Al-Yamani, A.A., and E.J. McCluskey, "BIST-Guided ATPG," 6th IEEE International Symposium on Quality Electronics Design (ISQED'05), San Jose, CA, March 21-23, 2005.
Al-Yamani, A.A., Erik Chmelar and Mikhail Grinchuk, "Segmented Addressable Scan Architecture," 23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005.
Park, I., A. Al-Yamani, and E.J. McCluskey, "Effective TARO Pattern Generation," 23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005.
Al-Yamani, A.A., N. Devta-Prasanna, and A. Gunda, "Should Illinois-Scan Architectures be Centralized or Distributed?," IEEE International Symposium on Defect and Fault Tolerance (DFT’05), Monterey, CA, Oct 3-5, 05.
Al-Yamani, A.A., and E.J. McCluskey, "Test Chip Experimental Results on High Level Structural Test," ACM Transactions on Design Automation of Electronic Systems (TODAES’05), October 2005.
Al-Yamani, A.A., "DFT for Controlled-Impedance IO Buffers," 43rd ACM/IEEE Design Automation Conference (DAC'06), San Francisco, CA, July 24-26, 2006.